prev_cmp_pp.qmsg

DES加密算法的VHDL实现,采用流水线技术实现

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X25_Y39 X36_Y51 " "Info: The peak interconnect region extends from location X25_Y39 to location X36_Y51" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "ITAPI_TAPI_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "EP3SL50F484C2 " "Warning: Timing characteristics of device EP3SL50F484C2 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0 "" 0}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_FIOMGR_MUST_USE_EXTERNAL_CLAMPING_DIODE_TOP_LEVEL" "23 " "Warning: Following 23 pins must use external clamping diodes." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "pi\[22\] 2.5 V K3 " "Info: Pin pi\[22\] uses I/O standard 2.5 V at K3" {  } { { "pp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pp.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[22] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "pi\[6\] 2.5 V J20 " "Info: Pin pi\[6\] uses I/O standard 2.5 V at J20" {  } { { "pp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pp.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[6] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "pi\[13\] 2.5 V C22 " "Info: Pin pi\[13\] uses I/O standard 2.5 V at C22" {  } { { "pp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pp.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[13] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "pi\[9\] 2.5 V P16 " "Info: Pin pi\[9\] uses I/O standard 2.5 V at P16" {  } { { "pp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pp.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[9] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "pi\[3\] 2.5 V N22 " "Info: Pin pi\[3\] uses I/O standard 2.5 V at N22" {  } { { "pp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pp.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[3] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "pi\[27\] 2.5 V H19 " "Info: Pin pi\[27\] uses I/O standard 2.5 V at H19" {  } { { "pp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pp.vhd" 6 -1 0 } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[27] } "NODE_NAME" } } { "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera quartus ii 7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { pi[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "" 0} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "pi\[32\] 2.5 V A19 " "Info: Pin pi\[32\] uses I/O standard 2.5 V at A19" {  } { { "pp.vhd" "" { Text "E:/Muxplux/Vhdl/DES/pp.vhd" 6 -1 0 } } { "e:/alt