keysch.fit.summary

DES加密算法的VHDL实现,采用流水线技术实现

Fitter Status : Successful - Sun Aug 05 21:22:04 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : keysch
Top-level Entity Name : keysch
Family : Stratix III
Device : EP3SL200F1517C2
Timing Models : Preliminary
Logic utilization : 0 %
    Combinational ALUTs : 0 / 159,120 ( 0 % )
    Memory ALUTs : 0 / 79,560 ( 0 % )
    Dedicated logic registers : 0 / 159,120 ( 0 % )
Total registers : 0
Total pins : 832 / 880 ( 95 % )
Total virtual pins : 0
Total block memory bits : 0 / 7,852,032 ( 0 % )
DSP block 18-bit elements : 0 / 576 ( 0 % )
Total PLLs : 0 / 12 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )