pc2.map.rpt

DES加密算法的VHDL实现,采用流水线技术实现

; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; pc2.vhd                          ; yes             ; User VHDL File  ; E:/Muxplux/Vhdl/DES/pc2.vhd  ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 0     ;
;     -- Combinational with no register       ; 0     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 0     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 104   ;
; Maximum fan-out node                        ; d[4]  ;
; Maximum fan-out                             ; 1     ;
; Total fan-out                               ; 48    ;
; Average fan-out                             ; 0.46  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |pc2                       ; 0 (0)       ; 0            ; 0           ; 104  ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |pc2                ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Aug 04 19:03:03 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pc2 -c pc2
Info: Found 2 design units, including 1 entities, in source file pc2.vhd
    Info: Found design unit 1: pc2-arch_pc2
    Info: Found entity 1: pc2
Info: Elaborating entity "pc2" for the top level hierarchy
Warning: Design contains 8 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "c[25]"
    Warning: No output dependent on input pin "c[22]"
    Warning: No output dependent on input pin "c[18]"
    Warning: No output dependent on input pin "c[9]"
    Warning: No output dependent on input pin "d[26]"
    Warning: No output dependent on input pin "d[15]"
    Warning: No output dependent on input pin "d[10]"
    Warning: No output dependent on input pin "d[7]"
Info: Implemented 104 device resources after synthesis - the final resource count might be different
    Info: Implemented 56 input pins
    Info: Implemented 48 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Allocated 148 megabytes of memory during processing
    Info: Processing ended: Sat Aug 04 19:03:08 2007
    Info: Elapsed time: 00:00:05