des_ip.vhd

DES加密算法的VHDL实现,采用流水线技术实现

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY DES_IP IS 
	port
	(
		din :  IN  STD_LOGIC_VECTOR(1 to 64);
		key :  IN  STD_LOGIC_VECTOR(1 to 64);
		dout :  OUT  STD_LOGIC_VECTOR(1 to 64)
	);
END DES_IP;

ARCHITECTURE bdf_type OF DES_IP IS 

component rr
	PORT(ka : IN STD_LOGIC_VECTOR(1 to 48);
		 l : IN STD_LOGIC_VECTOR(1 to 32);
		 r : IN STD_LOGIC_VECTOR(1 to 32);
		 rr : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component fp
	PORT(l : IN STD_LOGIC_VECTOR(1 to 32);
		 r : IN STD_LOGIC_VECTOR(1 to 32);
		 ct : OUT STD_LOGIC_VECTOR(1 to 64)
	);
end component;

component ip
	PORT(din : IN STD_LOGIC_VECTOR(1 to 64);
		 l0x : OUT STD_LOGIC_VECTOR(1 to 32);
		 r0x : OUT STD_LOGIC_VECTOR(1 to 32)
	);
end component;

component keysch
	PORT(key : IN STD_LOGIC_VECTOR(1 to 64);
		 k10x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k11x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k12x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k13x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k14x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k15x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k16x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k1x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k2x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k3x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k4x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k5x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k6x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k7x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k8x : OUT STD_LOGIC_VECTOR(1 to 48);
		 k9x : OUT STD_LOGIC_VECTOR(1 to 48)
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(1 to 32);
signal	SYNTHESIZED_WIRE_50 :  STD_LOGIC_VECTOR(1 to 32);
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_51 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_52 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_53 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_9 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_54 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_12 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_55 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_15 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_56 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_18 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_57 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_21 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_58 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_24 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_59 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_28 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_29 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_60 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_32 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_61 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_35 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_62 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_38 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_63 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_41 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_64 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_44 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_65 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_47 :  STD_LOGIC_VECTOR(1 to 48);


BEGIN 



b2v_inst1 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_0,
		 l => SYNTHESIZED_WIRE_1,
		 r => SYNTHESIZED_WIRE_50,
		 rr => SYNTHESIZED_WIRE_60);

b2v_inst10 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_3,
		 l => SYNTHESIZED_WIRE_51,
		 r => SYNTHESIZED_WIRE_52,
		 rr => SYNTHESIZED_WIRE_53);

b2v_inst11 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_6,
		 l => SYNTHESIZED_WIRE_52,
		 r => SYNTHESIZED_WIRE_53,
		 rr => SYNTHESIZED_WIRE_54);

b2v_inst12 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_9,
		 l => SYNTHESIZED_WIRE_53,
		 r => SYNTHESIZED_WIRE_54,
		 rr => SYNTHESIZED_WIRE_55);

b2v_inst13 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_12,
		 l => SYNTHESIZED_WIRE_54,
		 r => SYNTHESIZED_WIRE_55,
		 rr => SYNTHESIZED_WIRE_56);

b2v_inst14 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_15,
		 l => SYNTHESIZED_WIRE_55,
		 r => SYNTHESIZED_WIRE_56,
		 rr => SYNTHESIZED_WIRE_57);

b2v_inst15 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_18,
		 l => SYNTHESIZED_WIRE_56,
		 r => SYNTHESIZED_WIRE_57,
		 rr => SYNTHESIZED_WIRE_58);

b2v_inst16 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_21,
		 l => SYNTHESIZED_WIRE_57,
		 r => SYNTHESIZED_WIRE_58,
		 rr => SYNTHESIZED_WIRE_59);

b2v_inst17 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_24,
		 l => SYNTHESIZED_WIRE_58,
		 r => SYNTHESIZED_WIRE_59,
		 rr => SYNTHESIZED_WIRE_28);

b2v_inst18 : fp
PORT MAP(l => SYNTHESIZED_WIRE_59,
		 r => SYNTHESIZED_WIRE_28,
		 ct => dout);

b2v_inst19 : ip
PORT MAP(din => din,
		 l0x => SYNTHESIZED_WIRE_1,
		 r0x => SYNTHESIZED_WIRE_50);

b2v_inst2 : keysch
PORT MAP(key => key,
		 k10x => SYNTHESIZED_WIRE_6,
		 k11x => SYNTHESIZED_WIRE_9,
		 k12x => SYNTHESIZED_WIRE_12,
		 k13x => SYNTHESIZED_WIRE_15,
		 k14x => SYNTHESIZED_WIRE_18,
		 k15x => SYNTHESIZED_WIRE_21,
		 k16x => SYNTHESIZED_WIRE_24,
		 k1x => SYNTHESIZED_WIRE_0,
		 k2x => SYNTHESIZED_WIRE_29,
		 k3x => SYNTHESIZED_WIRE_32,
		 k4x => SYNTHESIZED_WIRE_35,
		 k5x => SYNTHESIZED_WIRE_38,
		 k6x => SYNTHESIZED_WIRE_41,
		 k7x => SYNTHESIZED_WIRE_44,
		 k8x => SYNTHESIZED_WIRE_47,
		 k9x => SYNTHESIZED_WIRE_3);

b2v_inst3 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_29,
		 l => SYNTHESIZED_WIRE_50,
		 r => SYNTHESIZED_WIRE_60,
		 rr => SYNTHESIZED_WIRE_61);

b2v_inst4 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_32,
		 l => SYNTHESIZED_WIRE_60,
		 r => SYNTHESIZED_WIRE_61,
		 rr => SYNTHESIZED_WIRE_62);

b2v_inst5 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_35,
		 l => SYNTHESIZED_WIRE_61,
		 r => SYNTHESIZED_WIRE_62,
		 rr => SYNTHESIZED_WIRE_63);

b2v_inst6 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_38,
		 l => SYNTHESIZED_WIRE_62,
		 r => SYNTHESIZED_WIRE_63,
		 rr => SYNTHESIZED_WIRE_64);

b2v_inst7 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_41,
		 l => SYNTHESIZED_WIRE_63,
		 r => SYNTHESIZED_WIRE_64,
		 rr => SYNTHESIZED_WIRE_65);

b2v_inst8 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_44,
		 l => SYNTHESIZED_WIRE_64,
		 r => SYNTHESIZED_WIRE_65,
		 rr => SYNTHESIZED_WIRE_51);

b2v_inst9 : rr
PORT MAP(ka => SYNTHESIZED_WIRE_47,
		 l => SYNTHESIZED_WIRE_65,
		 r => SYNTHESIZED_WIRE_51,
		 rr => SYNTHESIZED_WIRE_52);

END;