des_ip.map.rpt

DES加密算法的VHDL实现,采用流水线技术实现

;       |ep_xor_key:b2v_inst1| ; 48 (48)     ; 0            ; 0           ; 0    ; 0            ; 48 (48)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst5|ep_xor_key:b2v_inst1  ; work         ;
;       |sbox:b2v_inst5|       ; 188 (188)   ; 0            ; 0           ; 0    ; 0            ; 188 (188)    ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst5|sbox:b2v_inst5        ; work         ;
;    |RR:inst6|                ; 248 (0)     ; 0            ; 0           ; 0    ; 0            ; 248 (0)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst6                       ; work         ;
;       |LxorR:b2v_inst3|      ; 12 (12)     ; 0            ; 0           ; 0    ; 0            ; 12 (12)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst6|LxorR:b2v_inst3       ; work         ;
;       |ep_xor_key:b2v_inst1| ; 48 (48)     ; 0            ; 0           ; 0    ; 0            ; 48 (48)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst6|ep_xor_key:b2v_inst1  ; work         ;
;       |sbox:b2v_inst5|       ; 188 (188)   ; 0            ; 0           ; 0    ; 0            ; 188 (188)    ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst6|sbox:b2v_inst5        ; work         ;
;    |RR:inst7|                ; 253 (0)     ; 0            ; 0           ; 0    ; 0            ; 253 (0)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst7                       ; work         ;
;       |LxorR:b2v_inst3|      ; 27 (27)     ; 0            ; 0           ; 0    ; 0            ; 27 (27)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst7|LxorR:b2v_inst3       ; work         ;
;       |ep_xor_key:b2v_inst1| ; 48 (48)     ; 0            ; 0           ; 0    ; 0            ; 48 (48)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst7|ep_xor_key:b2v_inst1  ; work         ;
;       |sbox:b2v_inst5|       ; 178 (178)   ; 0            ; 0           ; 0    ; 0            ; 178 (178)    ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst7|sbox:b2v_inst5        ; work         ;
;    |RR:inst8|                ; 236 (0)     ; 0            ; 0           ; 0    ; 0            ; 236 (0)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst8                       ; work         ;
;       |ep_xor_key:b2v_inst1| ; 48 (48)     ; 0            ; 0           ; 0    ; 0            ; 48 (48)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst8|ep_xor_key:b2v_inst1  ; work         ;
;       |sbox:b2v_inst5|       ; 188 (188)   ; 0            ; 0           ; 0    ; 0            ; 188 (188)    ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst8|sbox:b2v_inst5        ; work         ;
;    |RR:inst9|                ; 236 (0)     ; 0            ; 0           ; 0    ; 0            ; 236 (0)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst9                       ; work         ;
;       |ep_xor_key:b2v_inst1| ; 48 (48)     ; 0            ; 0           ; 0    ; 0            ; 48 (48)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst9|ep_xor_key:b2v_inst1  ; work         ;
;       |sbox:b2v_inst5|       ; 188 (188)   ; 0            ; 0           ; 0    ; 0            ; 188 (188)    ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DES_IP|RR:inst9|sbox:b2v_inst5        ; work         ;
+------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Wed May 06 10:24:07 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DES_IP -c DES_IP
Info: Found 1 design units, including 1 entities, in source file DES_IP.bdf
    Info: Found entity 1: DES_IP
Info: Elaborating entity "DES_IP" for the top level hierarchy
Warning: Using design file fp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fp-arch_fp
    Info: Found entity 1: fp
Info: Elaborating entity "fp" for hierarchy "fp:inst18"
Warning: Using design file RR.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: RR-bdf_type
    Info: Found entity 1: RR
Warning (12300): Found the following files while searching for definition of entity "RR", but did not use these files because already using a different file containing the entity definition
    Warning: File: RR.bdf
Info: Elaborating entity "RR" for hierarchy "RR:inst16"
Warning: Using design file ep.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ep-arch_ep
    Info: Found entity 1: ep
Info: Elaborating entity "ep" for hierarchy "RR:inst16|ep:b2v_inst"
Warning: Using design file ep_xor_key.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ep_xor_key-arch_ep_xor_key
    Info: Found entity 1: ep_xor_key
Info: Elaborating entity "ep_xor_key" for hierarchy "RR:inst16|ep_xor_key:b2v_inst1"
Warning: Using design file pp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: pp-arch_pp
    Info: Found entity 1: pp
Info: Elaborating entity "pp" for hierarchy "RR:inst16|pp:b2v_inst2"
Warning: Using design file lxorr.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: LxorR-arch_LxorR
    Info: Found entity 1: LxorR
Info: Elaborating entity "lxorr" for hierarchy "RR:inst16|lxorr:b2v_inst3"
Warning: Using design file sbox.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sbox-arch_sbox
    Info: Found entity 1: sbox
Info: Elaborating entity "sbox" for hierarchy "RR:inst16|sbox:b2v_inst5"
Warning: Using design file keysch.vhd, which is not specified as a design file for the current project, but contains definitions for 6 design units and 3 entities in project
    Info: Found design unit 1: pc1-arch_pc1
    Info: Found design unit 2: pc2-arch_pc2
    Info: Found design unit 3: keysch-arch_keysch
    Info: Found entity 1: pc1
    Info: Found entity 2: pc2
    Info: Found entity 3: keysch
Info: Elaborating entity "keysch" for hierarchy "keysch:inst2"
Info: Elaborating entity "pc1" for hierarchy "keysch:inst2|pc1:pc_1"
Info: Elaborating entity "pc2" for hierarchy "keysch:inst2|pc2:key1"
Warning: Using design file ip.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ip-arch_ip
    Info: Found entity 1: ip
Info: Elaborating entity "ip" for hierarchy "ip:inst19"
Warning: Design contains 8 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "key[8]"
    Warning (15610): No output dependent on input pin "key[16]"
    Warning (15610): No output dependent on input pin "key[24]"
    Warning (15610): No output dependent on input pin "key[32]"
    Warning (15610): No output dependent on input pin "key[40]"
    Warning (15610): No output dependent on input pin "key[48]"
    Warning (15610): No output dependent on input pin "key[56]"
    Warning (15610): No output dependent on input pin "key[64]"
Info: Implemented 4160 device resources after synthesis - the final resource count might be different
    Info: Implemented 128 input pins
    Info: Implemented 64 output pins
    Info: Implemented 3968 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
    Info: Peak virtual memory: 180 megabytes
    Info: Processing ended: Wed May 06 10:29:04 2009
    Info: Elapsed time: 00:04:57
    Info: Total CPU time (on all processors): 00:04:56