enlxorr.map.rpt

DES加密算法的VHDL实现,采用流水线技术实现

Analysis & Synthesis report for enLxorR
Mon Aug 06 16:11:37 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                             ;
+-------------------------------+------------------------------------------+
; Analysis & Synthesis Status   ; Successful - Mon Aug 06 16:11:37 2007    ;
; Quartus II Version            ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name                 ; enLxorR                                  ;
; Top-level Entity Name         ; enLxorR                                  ;
; Family                        ; Stratix III                              ;
; Logic utilization             ; N/A                                      ;
;     Combinational ALUTs       ; 32                                       ;
;     Memory ALUTs              ; 0                                        ;
;     Dedicated logic registers ; 0                                        ;
; Total registers               ; 0                                        ;
; Total pins                    ; 96                                       ;
; Total virtual pins            ; 0                                        ;
; Total block memory bits       ; 0                                        ;
; DSP block 18-bit elements     ; 0                                        ;
; Total PLLs                    ; 0                                        ;
; Total DLLs                    ; 0                                        ;
+-------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                         ;
+-----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                      ; Setting            ; Default Value      ;
+-----------------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name                                                       ; enLxorR            ; enLxorR            ;
; Family name                                                                 ; Stratix III        ; Stratix II         ;
; Restructure Multiplexers                                                    ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                         ; Off                ; Off                ;
; Preserve fewer node names                                                   ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                   ; Off                ; Off                ;
; Verilog Version                                                             ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                    ; Auto               ; Auto               ;
; Safe State Machine                                                          ; Off                ; Off                ;
; Extract Verilog State Machines                                              ; On                 ; On                 ;
; Extract VHDL State Machines                                                 ; On                 ; On                 ;
; Ignore Verilog initial constructs                                           ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                     ; On                 ; On                 ;
; DSP Block Balancing                                                         ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                          ; On                 ; On                 ;
; Power-Up Don't Care                                                         ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                ; Off                ; Off                ;
; Remove Duplicate Registers                                                  ; On                 ; On                 ;
; Ignore CARRY Buffers                                                        ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                      ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                   ; Off                ; Off                ;
; Ignore LCELL Buffers                                                        ; Off                ; Off                ;
; Ignore SOFT Buffers                                                         ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                              ; Off                ; Off                ;
; Optimization Technique -- Stratix II/III/HardCopy II/Stratix II GX/Arria GX ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix II/Stratix III                                ; 70                 ; 70                 ;
; Auto Carry Chains                                                           ; On                 ; On                 ;
; Auto Open-Drain Pins                                                        ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                       ; Off                ; Off                ;
; Perform gate-level register retiming                                        ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                      ; On                 ; On                 ;
; Auto ROM Replacement                                                        ; On                 ; On                 ;
; Auto RAM Replacement                                                        ; On                 ; On                 ;
; Auto DSP Block Replacement                                                  ; On                 ; On                 ;
; Auto Shift Register Replacement                                             ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                               ; On                 ; On                 ;
; Allow Synchronous Control Signals                                           ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                      ; Off                ; Off                ;
; Auto RAM Block Balancing                                                    ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                           ; Off                ; Off                ;
; Auto Resource Sharing                                                       ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                          ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                          ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                               ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                           ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                          ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                          ; Off                ; Off                ;