des_ip.flow.rpt

DES加密算法的VHDL实现,采用流水线技术实现

Flow report for DES_IP
Wed May 06 10:29:59 2009
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Flow Summary                                                             ;
+--------------------------+-----------------------------------------------+
; Flow Status              ; Successful - Wed May 06 10:29:59 2009         ;
; Quartus II Version       ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ;
; Revision Name            ; DES_IP                                        ;
; Top-level Entity Name    ; DES_IP                                        ;
; Family                   ; Cyclone                                       ;
; Device                   ; EP1C20F400C8                                  ;
; Timing Models            ; Final                                         ;
; Met timing requirements  ; Yes                                           ;
; Total logic elements     ; 3,968 / 20,060 ( 20 % )                       ;
; Total pins               ; 192 / 301 ( 64 % )                            ;
; Total virtual pins       ; 0                                             ;
; Total memory bits        ; 0 / 294,912 ( 0 % )                           ;
; DSP block 9-bit elements ; N/A until Partition Merge                     ;
; Total PLLs               ; 0 / 2 ( 0 % )                                 ;
; Total DLLs               ; N/A until Partition Merge                     ;
+--------------------------+-----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 05/06/2009 10:24:07 ;
; Main task         ; Compilation         ;
; Revision Name     ; DES_IP              ;
+-------------------+---------------------+


+-------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                ;
+------------------------+-----------------------------+---------------+-------------+------------+
; Assignment Name        ; Value                       ; Default Value ; Entity Name ; Section Id ;
+------------------------+-----------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID  ; 95404132777.124157664703796 ; --            ; --          ; --         ;
; PARTITION_COLOR        ; 14622752                    ; --            ; --          ; Top        ;
; PARTITION_NETLIST_TYPE ; SOURCE                      ; --            ; --          ; Top        ;
+------------------------+-----------------------------+---------------+-------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis    ; 00:04:54     ; 1.0                     ; 180 MB              ; 00:04:53                           ;
; Fitter                  ; 00:00:36     ; 1.0                     ; 199 MB              ; 00:00:35                           ;
; Assembler               ; 00:00:05     ; 1.0                     ; 179 MB              ; 00:00:05                           ;
; Classic Timing Analyzer ; 00:00:03     ; 1.0                     ; 124 MB              ; 00:00:03                           ;
; Total                   ; 00:05:38     ; --                      ; --                  ; 00:05:36                           ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off DES_IP -c DES_IP
quartus_fit --read_settings_files=off --write_settings_files=off DES_IP -c DES_IP
quartus_asm --read_settings_files=off --write_settings_files=off DES_IP -c DES_IP
quartus_tan --read_settings_files=off --write_settings_files=off DES_IP -c DES_IP --timing_analysis_only