keysch.qdf

DES加密算法的VHDL实现,采用流水线技术实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity keysch is
port( key :	in 		std_logic_vector( 1 to 64 );
		k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x
		: 		out std_logic_vector( 1 to 48 )
	);
end entity keysch ;
architecture arch_keysch of keysch is
signal c0x,d0x,c1x,d1x,c2x,d2x,c3x,d3x,c4x,d4x,c5x,d5x,c6x,d6x,c7x,d7x,c8x,d8x,c9x,d9x,
		c10x,d10x,c11x,d11x,c12x,d12x,c13x,d13x,c14x,d14x,c15x,d15x,c16x,d16x
			: 		std_logic_vector( 1 to 28 );
component pc1 
port( 	key : 	  in 	std_logic_vector( 1 to 64 ) ;
		c0x,d0x : out 	std_logic_vector( 1 to 28 ) 
	);
end component pc1 ;
component pc2 
port( c,d : in 	std_logic_vector( 1 to 28 );
		ct: out std_logic_vector( 1 to 48 )
	);
end component pc2 ;
begin
	pc_1 : pc1 	port	map( key,c0x,d0x );
	
	c1x <= to_stdlogicvector(to_bitvector( c0x ) 	rol	1 ) ;
	d1x <= to_stdlogicvector(to_bitvector( c0x ) 	rol	1 ) ;
	
	c2x <= to_stdlogicvector(to_bitvector( c1x ) 	rol	1 ) ;
	d2x <= to_stdlogicvector(to_bitvector( c1x ) 	rol	1 ) ;
	
	c3x <= to_stdlogicvector(to_bitvector( c2x ) 	rol	2 ) ;
	d3x <= to_stdlogicvector(to_bitvector( c2x ) 	rol	2 ) ;
	
	c4x <= to_stdlogicvector(to_bitvector( c3x ) 	rol	2 ) ;
	d4x <= to_stdlogicvector(to_bitvector( c3x ) 	rol	2 ) ;
	
	c5x <= to_stdlogicvector(to_bitvector( c4x ) 	rol	2 ) ;
	d5x <= to_stdlogicvector(to_bitvector( c4x ) 	rol	2 ) ;
	
	c6x <= to_stdlogicvector(to_bitvector( c5x ) 	rol	2 ) ;
	d6x <= to_stdlogicvector(to_bitvector( c5x ) 	rol	2 ) ;
	
	c7x <= to_stdlogicvector(to_bitvector( c6x ) 	rol	2 ) ;
	d7x <= to_stdlogicvector(to_bitvector( c6x ) 	rol	2 ) ;
	
	c8x <= to_stdlogicvector(to_bitvector( c7x ) 	rol	2 ) ;
	d8x <= to_stdlogicvector(to_bitvector( c7x ) 	rol	2 ) ;
	
	c9x <= to_stdlogicvector(to_bitvector( c8x ) 	rol	1 ) ;
	d9x <= to_stdlogicvector(to_bitvector( c8x ) 	rol	1 ) ;
	
	c10x <= to_stdlogicvector(to_bitvector( c9x ) 	rol	2 ) ;
	d10x <= to_stdlogicvector(to_bitvector( c9x ) 	rol	2 ) ;
	
	c11x <= to_stdlogicvector(to_bitvector( c10x ) 	rol	2 ) ;
	d11x <= to_stdlogicvector(to_bitvector( c10x ) 	rol	2 ) ;
	
	c12x <= to_stdlogicvector(to_bitvector( c11x ) 	rol	2 ) ;
	d12x <= to_stdlogicvector(to_bitvector( c11x ) 	rol	2 ) ;
	
	c13x <= to_stdlogicvector(to_bitvector( c12x ) 	rol	2 ) ;
	d13x <= to_stdlogicvector(to_bitvector( c12x ) 	rol	2 ) ;
	
	c14x <= to_stdlogicvector(to_bitvector( c13x ) 	rol	2 ) ;
	d14x <= to_stdlogicvector(to_bitvector( c13x ) 	rol	2 ) ;
	
	c15x <= to_stdlogicvector(to_bitvector( c14x ) 	rol	2 ) ;
	d15x <= to_stdlogicvector(to_bitvector( c14x ) 	rol	2 ) ;
	
	c16x <= to_stdlogicvector(to_bitvector( c15x ) 	rol	1 ) ;
	d16x <= to_stdlogicvector(to_bitvector( c15x ) 	rol	1 ) ;
	
	key1 : pc2	port	map( c1x , d1x , k1x ) ;
	key2 : pc2	port	map( c2x , d2x , k2x ) ;
	key3 : pc2	port	map( c3x , d3x , k3x ) ;
	
	key4 : pc2	port	map( c4x , d4x , k4x ) ;
	key5 : pc2	port	map( c5x , d5x , k5x ) ;
	key6 : pc2	port	map( c6x , d6x , k6x ) ;
	
	key7 : pc2	port	map( c7x , d7x , k7x ) ;
	key8 : pc2	port	map( c8x , d8x , k8x ) ;
	key9 : pc2	port	map( c9x , d9x , k9x ) ;
	
	key10 : pc2	port	map( c10x , d10x , k10x ) ;
	key11 : pc2	port	map( c11x , d11x , k11x ) ;
	key12 : pc2	port	map( c12x , d12x , k12x ) ;
	
	key13 : pc2	port	map( c13x , d13x , k13x ) ;
	key14 : pc2	port	map( c14x , d14x , k14x ) ;
	key15 : pc2	port	map( c15x , d15x , k15x ) ;
	
	key16 : pc2	port	map( c16x , d16x , k16x ) ;
	
end architecture arch_keysch ;