prev_cmp_ep.qmsg

来自「DES加密算法的VHDL实现,采用流水线技术实现」· QMSG 代码 · 共 35 行 · 第 1/5 页

{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ep.sdc " "Critical Warning: SDC file not found: 'ep.sdc'" {  } {  } 1 0 "SDC file not found: '%1!s!'" 0 0 "" 0}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "Info: No base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 0 "No %1!s! found in the design. Calling %2!s!" 0 0 "" 0}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "Warning: No clocks defined in design." {  } {  } 0 0 "No clocks defined in design." 0 0 "" 0}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}