fp.fit.rpt

DES加密算法的VHDL实现,采用流水线技术实现

Fitter report for fp
Sat Aug 04 15:39:31 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Non-Global High Fan-Out Signals
 15. Interconnect Usage Summary
 16. Fitter Device Options
 17. Advanced Data - General
 18. Advanced Data - Placement Preparation
 19. Advanced Data - Placement
 20. Advanced Data - Routing
 21. Fitter Messages
 22. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Sat Aug 04 15:39:31 2007    ;
; Quartus II Version    ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name         ; fp                                       ;
; Top-level Entity Name ; fp                                       ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C4F324C6                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 0 / 4,000 ( 0 % )                        ;
; Total pins            ; 128 / 249 ( 51 % )                       ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0 / 78,336 ( 0 % )                       ;
; Total PLLs            ; 0 / 2 ( 0 % )                            ;
+-----------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; AUTO                           ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;