enll.map.rpt

DES加密算法的VHDL实现,采用流水线技术实现

+----------------------------------+-----------------+------------------------------------+------------------------------------+
; ENLL.bdf                         ; yes             ; User Block Diagram/Schematic File  ; E:/Muxplux/Vhdl/DES/ENLL.bdf       ;
; enLxorR.vhd                      ; yes             ; Other                              ; E:/Muxplux/Vhdl/DES/enLxorR.vhd    ;
; pp.vhd                           ; yes             ; Other                              ; E:/Muxplux/Vhdl/DES/pp.vhd         ;
; sbox.vhd                         ; yes             ; Other                              ; E:/Muxplux/Vhdl/DES/sbox.vhd       ;
; ep_xor_key.vhd                   ; yes             ; Other                              ; E:/Muxplux/Vhdl/DES/ep_xor_key.vhd ;
; ep.vhd                           ; yes             ; Other                              ; E:/Muxplux/Vhdl/DES/ep.vhd         ;
+----------------------------------+-----------------+------------------------------------+------------------------------------+


+-------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                             ;
+-----------------------------------------------+-------------------------+
; Resource                                      ; Usage                   ;
+-----------------------------------------------+-------------------------+
; Estimated ALUTs Used                          ; 112                     ;
;     -- Combinational ALUTs                    ; 112                     ;
;     -- Memory ALUTs                           ; 0                       ;
;     -- LUT_REGs                               ; 0                       ;
; Dedicated logic registers                     ; 0                       ;
;                                               ;                         ;
; Estimated ALUTs Unavailable                   ; 22                      ;
;     -- Due to unpartnered combinational logic ; 22                      ;
;     -- Due to Memory ALUTs                    ; 0                       ;
;     -- Due to LUT_REGs                        ; 0                       ;
;                                               ;                         ;
; Total combinational functions                 ; 112                     ;
; Combinational ALUT usage by number of inputs  ;                         ;
;     -- 7 input functions                      ; 0                       ;
;     -- 6 input functions                      ; 32                      ;
;     -- 5 input functions                      ; 0                       ;
;     -- 4 input functions                      ; 0                       ;
;     -- <=3 input functions                    ; 80                      ;
;                                               ;                         ;
; Combinational ALUTs by mode                   ;                         ;
;     -- normal mode                            ; 112                     ;
;     -- extended LUT mode                      ; 0                       ;
;     -- arithmetic mode                        ; 0                       ;
;     -- shared arithmetic mode                 ; 0                       ;
;                                               ;                         ;
; Estimated ALUT/register pairs used            ; 134                     ;
;                                               ;                         ;
; Total registers                               ; 0                       ;
;     -- Dedicated logic registers              ; 0                       ;
;     -- I/O registers                          ; 0                       ;
;     -- LUT_REGs                               ; 0                       ;
;                                               ;                         ;
; Estimated ALMs:  partially or completely used ; 67                      ;
;                                               ;                         ;
; I/O pins                                      ; 144                     ;
; Maximum fan-out node                          ; ep_xor_key:inst1|ct[23] ;
; Maximum fan-out                               ; 4                       ;
; Total fan-out                                 ; 528                     ;
; Average fan-out                               ; 1.32                    ;
+-----------------------------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                          ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 12x12 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name    ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+------------------------+--------------+
; |ENLL                      ; 112 (0)           ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 144  ; 0            ; |ENLL                  ; work         ;
;    |enLxorR:inst4|         ; 32 (32)           ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |ENLL|enLxorR:inst4    ; work         ;
;    |ep_xor_key:inst1|      ; 48 (48)           ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |ENLL|ep_xor_key:inst1 ; work         ;
;    |sbox:inst6|            ; 32 (32)           ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0         ; 0    ; 0            ; |ENLL|sbox:inst6       ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Aug 06 16:21:04 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ENLL -c ENLL
Info: Found 1 design units, including 1 entities, in source file ENLL.bdf
    Info: Found entity 1: ENLL
Info: Elaborating entity "ENLL" for the top level hierarchy
Warning: Using design file enLxorR.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: enLxorR-arch_enLxorR
    Info: Found entity 1: enLxorR
Info: Elaborating entity "enLxorR" for hierarchy "enLxorR:inst4"
Warning: Using design file pp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: pp-arch_pp
    Info: Found entity 1: pp
Info: Elaborating entity "pp" for hierarchy "pp:inst5"
Warning: Using design file sbox.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sbox-arch_sbox
    Info: Found entity 1: sbox
Info: Elaborating entity "sbox" for hierarchy "sbox:inst6"
Warning: Using design file ep_xor_key.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ep_xor_key-arch_ep_xor_key
    Info: Found entity 1: ep_xor_key
Info: Elaborating entity "ep_xor_key" for hierarchy "ep_xor_key:inst1"
Warning: Using design file ep.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ep-arch_ep
    Info: Found entity 1: ep
Info: Elaborating entity "ep" for hierarchy "ep:inst"
Info: Implemented 400 device resources after synthesis - the final resource count might be different
    Info: Implemented 112 input pins
    Info: Implemented 32 output pins
    Info: Implemented 112 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Allocated 149 megabytes of memory during processing
    Info: Processing ended: Mon Aug 06 16:21:10 2007
    Info: Elapsed time: 00:00:06