📄 endes.map.rpt
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; |ENLL:inst5| ; 80 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst5 ; work ;
; |ep_xor_key:b2v_inst1| ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst5|ep_xor_key:b2v_inst1 ; work ;
; |sbox:b2v_inst6| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst5|sbox:b2v_inst6 ; work ;
; |ENLL:inst6| ; 102 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst6 ; work ;
; |enLxorR:b2v_inst4| ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst6|enLxorR:b2v_inst4 ; work ;
; |ep_xor_key:b2v_inst1| ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst6|ep_xor_key:b2v_inst1 ; work ;
; |sbox:b2v_inst6| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst6|sbox:b2v_inst6 ; work ;
; |ENLL:inst7| ; 107 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst7 ; work ;
; |enLxorR:b2v_inst4| ; 27 (27) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst7|enLxorR:b2v_inst4 ; work ;
; |ep_xor_key:b2v_inst1| ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst7|ep_xor_key:b2v_inst1 ; work ;
; |sbox:b2v_inst6| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst7|sbox:b2v_inst6 ; work ;
; |ENLL:inst8| ; 112 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst8 ; work ;
; |enLxorR:b2v_inst4| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst8|enLxorR:b2v_inst4 ; work ;
; |ep_xor_key:b2v_inst1| ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst8|ep_xor_key:b2v_inst1 ; work ;
; |sbox:b2v_inst6| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst8|sbox:b2v_inst6 ; work ;
; |ENLL:inst9| ; 112 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst9 ; work ;
; |enLxorR:b2v_inst4| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst9|enLxorR:b2v_inst4 ; work ;
; |ep_xor_key:b2v_inst1| ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst9|ep_xor_key:b2v_inst1 ; work ;
; |sbox:b2v_inst6| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ENDES|ENLL:inst9|sbox:b2v_inst6 ; work ;
+------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+-----------+------+--------------+-----------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Tue Aug 07 11:09:14 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ENDES -c ENDES
Info: Found 2 design units, including 1 entities, in source file enLxorR.vhd
Info: Found design unit 1: enLxorR-arch_enLxorR
Info: Found entity 1: enLxorR
Info: Found 1 design units, including 1 entities, in source file ENDES.bdf
Info: Found entity 1: ENDES
Info: Found 2 design units, including 1 entities, in source file enfp.vhd
Info: Found design unit 1: enfp-arch_enfp
Info: Found entity 1: enfp
Info: Elaborating entity "ENDES" for the top level hierarchy
Info: Elaborating entity "enfp" for hierarchy "enfp:inst19"
Warning: Using design file ENLL.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: ENLL-bdf_type
Info: Found entity 1: ENLL
Warning: Found the following files while searching for definition of entity "ENLL", but did not use these files because already using a different file containing the entity definition
Warning: File: ENLL.bdf
Info: Elaborating entity "ENLL" for hierarchy "ENLL:inst17"
Warning: Using design file ep.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: ep-arch_ep
Info: Found entity 1: ep
Info: Elaborating entity "ep" for hierarchy "ENLL:inst17|ep:b2v_inst"
Warning: Using design file ep_xor_key.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: ep_xor_key-arch_ep_xor_key
Info: Found entity 1: ep_xor_key
Info: Elaborating entity "ep_xor_key" for hierarchy "ENLL:inst17|ep_xor_key:b2v_inst1"
Info: Elaborating entity "enLxorR" for hierarchy "ENLL:inst17|enLxorR:b2v_inst4"
Warning: Using design file pp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: pp-arch_pp
Info: Found entity 1: pp
Info: Elaborating entity "pp" for hierarchy "ENLL:inst17|pp:b2v_inst5"
Warning: Using design file sbox.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: sbox-arch_sbox
Info: Found entity 1: sbox
Info: Elaborating entity "sbox" for hierarchy "ENLL:inst17|sbox:b2v_inst6"
Warning: Using design file keysch.vhd, which is not specified as a design file for the current project, but contains definitions for 6 design units and 3 entities in project
Info: Found design unit 1: pc1-arch_pc1
Info: Found design unit 2: pc2-arch_pc2
Info: Found design unit 3: keysch-arch_keysch
Info: Found entity 1: pc1
Info: Found entity 2: pc2
Info: Found entity 3: keysch
Info: Elaborating entity "keysch" for hierarchy "keysch:inst2"
Info: Elaborating entity "pc1" for hierarchy "keysch:inst2|pc1:pc_1"
Info: Elaborating entity "pc2" for hierarchy "keysch:inst2|pc2:key1"
Warning: Using design file ip.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: ip-arch_ip
Info: Found entity 1: ip
Info: Elaborating entity "ip" for hierarchy "ip:inst"
Warning: Design contains 8 input pin(s) that do not drive logic
Warning: No output dependent on input pin "key[8]"
Warning: No output dependent on input pin "key[16]"
Warning: No output dependent on input pin "key[24]"
Warning: No output dependent on input pin "key[32]"
Warning: No output dependent on input pin "key[40]"
Warning: No output dependent on input pin "key[48]"
Warning: No output dependent on input pin "key[56]"
Warning: No output dependent on input pin "key[64]"
Info: Implemented 1841 device resources after synthesis - the final resource count might be different
Info: Implemented 128 input pins
Info: Implemented 64 output pins
Info: Implemented 1457 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
Info: Allocated 176 megabytes of memory during processing
Info: Processing ended: Tue Aug 07 11:10:36 2007
Info: Elapsed time: 00:01:22
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