keysch.vhd

DES加密算法的VHDL实现,采用流水线技术实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pc1 is
port( 	key : 	  in 	std_logic_vector( 1 to 64 ) ;
		c0x,d0x : out 	std_logic_vector( 1 to 28 ) 
	);
end entity pc1 ;
architecture arch_pc1 of pc1 is
begin
	c0x<=	key(57) & key(49) & key(41) & key(33) & key(25) & key(17) & key( 9) & key( 1) &
			key(58) & key(50) & key(42) & key(34) & key(26) & key(18) & key(10) & key( 2) &
			key(59) & key(51) & key(43) & key(35) & key(27) & key(19) & key(11) & key( 3) &
			key(60) & key(52) & key(44) & key(36) ;
	 
     d0x<= 	key(63) & key(55) & key(47) & key(39) & key(31) & key(23) & key(15) & key( 7) &
			key(62) & key(54) & key(46) & key(38) & key(30) & key(22) & key(14) & key( 6) &
			key(61) & key(53) & key(45) & key(37) & key(29) & key(21) & key(13) & key( 5) &
			key(28) & key(20) & key(12) & key( 4) ;
end architecture arch_pc1 ;




library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pc2 is
port( c,d : in 	std_logic_vector( 1 to 28 );
		ct: out std_logic_vector( 1 to 48 )
	);
end entity pc2 ;
architecture arch_pc2 of pc2 is
signal cd : 	std_logic_vector( 1 to 56 );
begin 
	cd <= 	c & d ;
	ct <=  cd(14) & cd(17) & cd(11) & cd(24) & cd( 1) & cd( 5) &
           cd( 3) & cd(28) & cd(15) & cd( 6) & cd(21) & cd(10) &
           cd(23) & cd(19) & cd(12) & cd( 4) & cd(26) & cd( 8) &
           cd(16) & cd( 7) & cd(27) & cd(20) & cd(13) & cd( 2) &
           cd(41) & cd(52) & cd(31) & cd(37) & cd(47) & cd(55) &
           cd(30) & cd(40) & cd(51) & cd(45) & cd(33) & cd(48) &
           cd(44) & cd(49) & cd(39) & cd(56) & cd(34) & cd(53) &
           cd(46) & cd(42) & cd(50) & cd(36) & cd(29) & cd(32) ;
end architecture arch_pc2 ;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity keysch is
port( key :	in 		std_logic_vector( 1 to 64 );
		k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x
		: 		out std_logic_vector( 1 to 48 )
	);
end entity keysch ;
architecture arch_keysch of keysch is
signal c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,
		c10x,c11x,c12x,c13x,c14x,c15x,c16x
			: 		std_logic_vector( 1 to 28 );
signal d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,
		d10x,d11x,d12x,d13x,d14x,d15x,d16x
			: 		std_logic_vector( 1 to 28 );			
component pc1 
port( 	key : 	  in 	std_logic_vector( 1 to 64 ) ;
		c0x,d0x : out 	std_logic_vector( 1 to 28 ) 
	);
end component pc1 ;
component pc2 
port( c,d : in 	std_logic_vector( 1 to 28 );
		ct: out std_logic_vector( 1 to 48 )
	);
end component pc2 ;
begin
	pc_1 : pc1 	port	map( key,c0x,d0x );
	
	c1x <= 	c0x( 2 to 28 ) & c0x( 1 )  ;
	d1x <=	d0x( 2 to 28 ) & d0x( 1 ) ;--shifts 1 bit.
	
	c2x <= 	c1x( 2 to 28 ) & c1x( 1 ) ; 
	d2x <=	d1x( 2 to 28 ) & d1x( 1 ) ;--shifts 1 bit.
		
	c3x <= 	c2x( 3 to 28 ) & c2x( 1 ) & c2x( 2 ) ; 
	d3x <=	d2x( 3 to 28 ) & d2x( 1 ) & d2x( 2 ) ;--shifts 2 bits.
		
	c4x <= 	c3x( 3 to 28 ) & c3x( 1 ) & c3x( 2 ) ; 
	d4x <=	d3x( 3 to 28 ) & d3x( 1 ) & d3x( 2 ) ;--shifts 2 bits.	
		
	c5x <= 	c4x( 3 to 28 ) & c4x( 1 ) & c4x( 2 ) ; 
	d5x <=	d4x( 3 to 28 ) & d4x( 1 ) & d4x( 2 ) ;--shifts 2 bits.	
		
	c6x <= 	c5x( 3 to 28 ) & c5x( 1 ) & c5x( 2 ) ; 
	d6x <=	d5x( 3 to 28 ) & d5x( 1 ) & d5x( 2 ) ;--shifts 2 bits.	
		
	c7x <= 	c6x( 3 to 28 ) & c6x( 1 ) & c6x( 2 ) ; 
	d7x <=	d6x( 3 to 28 ) & d6x( 1 ) & d6x( 2 ) ;--shifts 2 bits.	
		
	c8x <= 	c7x( 3 to 28 ) & c7x( 1 ) & c7x( 2 ) ; 
	d8x <=	d7x( 3 to 28 ) & d7x( 1 ) & d7x( 2 ) ;--shifts 2 bits.	
		
	c9x <= 	c8x( 2 to 28 ) & c8x( 1 ) ;
	d9x <=	d8x( 2 to 28 ) & d8x( 1 ) ;--shifts 1 bit.	
		
	c10x <= c9x( 3 to 28 ) & c9x( 1 ) & c9x( 2 ) ; 
	d10x <=	d9x( 3 to 28 ) & d9x( 1 ) & d9x( 2 ) ;--shifts 2 bits.	
		
	c11x <= c10x( 3 to 28 ) & c10x( 1 ) & c10x( 2 ) ; 
	d11x <=	d10x( 3 to 28 ) & d10x( 1 ) & d10x( 2 ) ;--shifts 2 bits.	
		
	c12x <= c11x( 3 to 28 ) & c11x( 1 ) & c11x( 2 ) ; 
	d12x <=	d11x( 3 to 28 ) & d11x( 1 ) & d11x( 2 ) ;--shifts 2 bits.	
		
	c13x <= c12x( 3 to 28 ) & c12x( 1 ) & c12x( 2 ) ; 
	d13x <=	d12x( 3 to 28 ) & d12x( 1 ) & d12x( 2 ) ;--shifts 2 bits.	
		
	c14x <= c13x( 3 to 28 ) & c13x( 1 ) & c13x( 2 ) ; 
	d14x <=	d13x( 3 to 28 ) & d13x( 1 ) & d13x( 2 ) ;--shifts 2 bits.	
		
	c15x <= c14x( 3 to 28 ) & c14x( 1 ) & c14x( 2 ) ; 
	d15x <=	d14x( 3 to 28 ) & d14x( 1 ) & d14x( 2 ) ;--shifts 2 bits.	
		
	c16x <= c15x( 2 to 28 ) & c15x( 1 ) ;
	d16x <=	d15x( 2 to 28 ) & d15x( 1 ) ;--shifts 1 bit.
		
	key1 : pc2	port	map( c1x , d1x , k1x ) ;
	key2 : pc2	port	map( c2x , d2x , k2x ) ;
	key3 : pc2	port	map( c3x , d3x , k3x ) ;
	
	key4 : pc2	port	map( c4x , d4x , k4x ) ;
	key5 : pc2	port	map( c5x , d5x , k5x ) ;
	key6 : pc2	port	map( c6x , d6x , k6x ) ;
	
	key7 : pc2	port	map( c7x , d7x , k7x ) ;
	key8 : pc2	port	map( c8x , d8x , k8x ) ;
	key9 : pc2	port	map( c9x , d9x , k9x ) ;
	
	key10 : pc2	port	map( c10x , d10x , k10x ) ;
	key11 : pc2	port	map( c11x , d11x , k11x ) ;
	key12 : pc2	port	map( c12x , d12x , k12x ) ;
	
	key13 : pc2	port	map( c13x , d13x , k13x ) ;
	key14 : pc2	port	map( c14x , d14x , k14x ) ;
	key15 : pc2	port	map( c15x , d15x , k15x ) ;
	
	key16 : pc2	port	map( c16x , d16x , k16x ) ;
	
end architecture arch_keysch ;