fp.fit.summary

DES加密算法的VHDL实现,采用流水线技术实现

Fitter Status : Successful - Sat Aug 04 15:39:31 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : fp
Top-level Entity Name : fp
Family : Cyclone
Device : EP1C4F324C6
Timing Models : Final
Total logic elements : 0 / 4,000 ( 0 % )
Total pins : 128 / 249 ( 51 % )
Total virtual pins : 0
Total memory bits : 0 / 78,336 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )