pc1.vhd

DES加密算法的VHDL实现,采用流水线技术实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pc1 is
port( 	key : 	  in 	std_logic_vector( 1 to 64 ) ;
		c0x,d0x : out 	std_logic_vector( 1 to 28 ) 
	);
end entity pc1 ;
architecture arch_pc1 of pc1 is
begin
	c0x<=	key(57) & key(49) & key(41) & key(33) & key(25) & key(17) & key( 9) & key( 1) &
			key(58) & key(50) & key(42) & key(34) & key(26) & key(18) & key(10) & key( 2) &
			key(59) & key(51) & key(43) & key(35) & key(27) & key(19) & key(11) & key( 3) &
			key(60) & key(52) & key(44) & key(36) ;
	 
     d0x<= 	key(63) & key(55) & key(47) & key(39) & key(31) & key(23) & key(15) & key( 7) &
			key(62) & key(54) & key(46) & key(38) & key(30) & key(22) & key(14) & key( 6) &
			key(61) & key(53) & key(45) & key(37) & key(29) & key(21) & key(13) & key( 5) &
			key(28) & key(20) & key(12) & key( 4) ;
end architecture arch_pc1 ;