ep.map.summary

来自「DES加密算法的VHDL实现,采用流水线技术实现」· SUMMARY 代码 · 共 17 行

Analysis & Synthesis Status : Successful - Sat Aug 04 21:14:23 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : ep
Top-level Entity Name : ep
Family : Stratix III
Logic utilization : N/A
    Combinational ALUTs : 0
    Memory ALUTs : 0
    Dedicated logic registers : 0
Total registers : 0
Total pins : 80
Total virtual pins : 0
Total block memory bits : 0
DSP block 18-bit elements : 0
Total PLLs : 0
Total DLLs : 0