des_ip.fit.rpt

来自「DES加密算法的VHDL实现,采用流水线技术实现」· RPT 代码 · 共 376 行 · 第 1/5 页

Fitter report for DES_IP
Wed May 06 10:29:42 2009
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Partition Preservation Settings
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Delay Chain Summary
 14. Pad To Core Delay Chain Fanout
 15. Non-Global High Fan-Out Signals
 16. Interconnect Usage Summary
 17. LAB Logic Elements
 18. LAB Signals Sourced
 19. LAB Signals Sourced Out
 20. LAB Distinct Inputs
 21. Fitter Device Options
 22. Advanced Data - General
 23. Advanced Data - Placement Preparation
 24. Advanced Data - Placement
 25. Advanced Data - Routing
 26. Fitter Messages
 27. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Fitter Summary                                                        ;
+-----------------------+-----------------------------------------------+
; Fitter Status         ; Successful - Wed May 06 10:29:42 2009         ;
; Quartus II Version    ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ;
; Revision Name         ; DES_IP                                        ;
; Top-level Entity Name ; DES_IP                                        ;
; Family                ; Cyclone                                       ;
; Device                ; EP1C20F400C8                                  ;
; Timing Models         ; Final                                         ;
; Total logic elements  ; 3,968 / 20,060 ( 20 % )                       ;
; Total pins            ; 192 / 301 ( 64 % )                            ;
; Total virtual pins    ; 0                                             ;
; Total memory bits     ; 0 / 294,912 ( 0 % )                           ;
; Total PLLs            ; 0 / 2 ( 0 % )                                 ;
+-----------------------+-----------------------------------------------+


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