enfp.fit.rpt

DES加密算法的VHDL实现,采用流水线技术实现

+-------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; AUTO                           ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Auto RAM to MLAB Conversion                                           ; On                             ; On                             ;
; Equivalent RAM and MLAB Power Up                                      ; Auto                           ; Auto                           ;
; Programmable Power Technology Optimization                            ; Automatic                      ; Automatic                      ;
; Programmable Power Maximum High-Speed Fraction of Used LAB Tiles      ; 1.0                            ; 1.0                            ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                              ; Auto                           ; Auto                           ;
; Auto Register Duplication                                             ; Auto                           ; Auto                           ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                    ;
+--------------------------------------------------------+-------------------------+
; Resource                                               ; Usage                   ;
+--------------------------------------------------------+-------------------------+
; ALUTs Used                                             ; 0 / 38,000 ( 0 % )      ;
;     -- Combinational ALUTs                             ; 0 / 38,000 ( 0 % )      ;
;     -- Memory ALUTs                                    ; 0 / 19,000 ( 0 % )      ;
;     -- LUT_REGs                                        ; 0 / 38,000 ( 0 % )      ;
; Dedicated logic registers                              ; 0 / 38,000 ( 0 % )      ;
;                                                        ;                         ;
; ALUTs Unavailable                                      ; 0                       ;
;     -- Due to unpartnered 7 input function             ; 0                       ;
;     -- Due to unpartnered 6 input function             ; 0                       ;
;     -- Due to Memory ALUTs                             ; 0                       ;
;     -- Due to LUT_REGs                                 ; 0                       ;
;                                                        ;                         ;
; Combinational ALUT usage by number of inputs           ;                         ;
;     -- 7 input functions                               ; 0                       ;
;     -- 6 input functions                               ; 0                       ;