enll.sta.rpt

DES加密算法的VHDL实现,采用流水线技术实现

TimeQuest Timing Analyzer report for ENLL
Mon Aug 06 16:22:05 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Board Trace Model Assignments
  4. Slow Corner Signal Integrity Metrics
  5. Setup Summary
  6. Hold Summary
  7. Recovery Summary
  8. Removal Summary
  9. Unconstrained Paths
 10. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                     ;
+--------------------+--------------------------------------------------+
; Quartus II Version ; Version 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name      ; ENLL                                             ;
; Device Family      ; Stratix III                                      ;
; Device Name        ; EP3SL50F484C2                                    ;
; Timing Models      ; Preliminary                                      ;
; Delay Model        ; Slow Model                                       ;
; Rise/Fall Delays   ; Enabled                                          ;
+--------------------+--------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                   ;
+--------+--------------+---------------+----------------+------------------+--------+--------------+--------------------+--------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin    ; I/O Standard ; Near Series R ; Near Pull-up R ; Near Pull-down R ; Near C ; Tline Length ; Tline L per Length ; Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+--------+--------------+---------------+----------------+------------------+--------+--------------+--------------------+--------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; ln[1]  ; 2.5 V        ; short         ; open           ; open             ; open   ; 0            ; 0                  ; 0                  ; short        ; open          ; open            ; open  ; 0                   ; -                  ;
; ln[2]  ; 2.5 V        ; short         ; open           ; open             ; open   ; 0            ; 0                  ; 0                  ; short        ; open          ; open            ; open  ; 0                   ; -                  ;
; ln[3]  ; 2.5 V        ; short         ; open           ; open             ; open   ; 0            ; 0                  ; 0                  ; short        ; open          ; open            ; open  ; 0                   ; -                  ;
; ln[4]  ; 2.5 V        ; short         ; open           ; open             ; open   ; 0            ; 0                  ; 0                  ; short        ; open          ; open            ; open  ; 0                   ; -                  ;
; ln[5]  ; 2.5 V        ; short         ; open           ; open             ; open   ; 0            ; 0                  ; 0                  ; short        ; open          ; open            ; open  ; 0                   ; -                  ;
; ln[6]  ; 2.5 V        ; short         ; open           ; open             ; open   ; 0            ; 0                  ; 0                  ; short        ; open          ; open            ; open  ; 0                   ; -                  ;
; ln[7]  ; 2.5 V        ; short         ; open           ; open             ; open   ; 0            ; 0                  ; 0                  ; short        ; open          ; open            ; open  ; 0                   ; -                  ;
; ln[8]  ; 2.5 V        ; short         ; open           ; open             ; open   ; 0            ; 0                  ; 0                  ; short        ; open          ; open            ; open  ; 0                   ; -                  ;
; ln[9]  ; 2.5 V        ; short         ; open           ; open             ; open   ; 0            ; 0                  ; 0                  ; short        ; open          ; open            ; open  ; 0                   ; -                  ;