endes.fit.summary

DES加密算法的VHDL实现,采用流水线技术实现

Fitter Status : Successful - Tue Aug 07 11:11:26 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : ENDES
Top-level Entity Name : ENDES
Family : Stratix III
Device : EP3SL50F484C2
Timing Models : Preliminary
Logic utilization : 4 %
    Combinational ALUTs : 1,457 / 38,000 ( 4 % )
    Memory ALUTs : 0 / 19,000 ( 0 % )
    Dedicated logic registers : 0 / 38,000 ( 0 % )
Total registers : 0
Total pins : 192 / 296 ( 65 % )
Total virtual pins : 0
Total block memory bits : 0 / 1,880,064 ( 0 % )
DSP block 18-bit elements : 0 / 216 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )