rr.vhd

DES加密算法的VHDL实现,采用流水线技术实现

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY RR IS 
	port
	(
		ka :  IN  STD_LOGIC_VECTOR(1 to 48);
		l :  IN  STD_LOGIC_VECTOR(1 to 32);
		r :  IN  STD_LOGIC_VECTOR(1 to 32);
		rr :  OUT  STD_LOGIC_VECTOR(31 downto 0)
	);
END RR;

ARCHITECTURE bdf_type OF RR IS 

component ep
	PORT(r : IN STD_LOGIC_VECTOR(1 to 32);
		 ct : OUT STD_LOGIC_VECTOR(1 to 48)
	);
end component;

component ep_xor_key
	PORT(ka : IN STD_LOGIC_VECTOR(1 to 48);
		 ra : IN STD_LOGIC_VECTOR(1 to 48);
		 ct : OUT STD_LOGIC_VECTOR(1 to 48)
	);
end component;

component pp
	PORT(pi : IN STD_LOGIC_VECTOR(1 to 32);
		 po : OUT STD_LOGIC_VECTOR(1 to 32)
	);
end component;

component lxorr
	PORT(l : IN STD_LOGIC_VECTOR(1 to 32);
		 r : IN STD_LOGIC_VECTOR(1 to 32);
		 ro : OUT STD_LOGIC_VECTOR(1 to 32)
	);
end component;

component sbox
	PORT(rs : IN STD_LOGIC_VECTOR(47 downto 0);
		 so : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(1 to 48);
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(1 to 32);
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(1 to 48);


BEGIN 



b2v_inst : ep
PORT MAP(r => r,
		 ct => SYNTHESIZED_WIRE_0);

b2v_inst1 : ep_xor_key
PORT MAP(ka => ka,
		 ra => SYNTHESIZED_WIRE_0,
		 ct => SYNTHESIZED_WIRE_3);

b2v_inst2 : pp
PORT MAP(pi => SYNTHESIZED_WIRE_1,
		 po => SYNTHESIZED_WIRE_2);

b2v_inst3 : lxorr
PORT MAP(l => l,
		 r => SYNTHESIZED_WIRE_2,
		 ro => rr);

b2v_inst5 : sbox
PORT MAP(rs => SYNTHESIZED_WIRE_3,
		 so => SYNTHESIZED_WIRE_1);

END;