📄 traffictrl.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
Device-Specific Information: c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
traffictrl
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC Row Col Primitive Code INP FBK OUT FBK Name
- 2 D 18 AND2 0 3 0 5 |DIVCLK:10|LPM_ADD_SUB:88|addcore:adder|:99
- 7 D 14 AND2 0 4 0 4 |DIVCLK:10|LPM_ADD_SUB:88|addcore:adder|:111
- 1 D 14 AND2 0 2 0 1 |DIVCLK:10|LPM_ADD_SUB:88|addcore:adder|:115
- 2 D 14 AND2 0 4 0 4 |DIVCLK:10|LPM_ADD_SUB:88|addcore:adder|:123
- 2 D 12 AND2 0 3 0 1 |DIVCLK:10|LPM_ADD_SUB:88|addcore:adder|:131
- 6 C 15 AND2 0 2 0 1 |DIVCLK:10|LPM_ADD_SUB:146|addcore:adder|:67
- 4 C 15 AND2 0 3 0 2 |DIVCLK:10|LPM_ADD_SUB:146|addcore:adder|:71
- 3 C 15 AND2 0 2 0 2 |DIVCLK:10|LPM_ADD_SUB:146|addcore:adder|:75
- 7 C 13 AND2 0 2 0 1 |DIVCLK:10|LPM_ADD_SUB:146|addcore:adder|:79
- 1 C 22 DFF 1 3 1 20 |DIVCLK:10|temp4 (|DIVCLK:10|:6)
- 8 C 22 DFF 1 4 0 2 |DIVCLK:10|counter42 (|DIVCLK:10|:10)
- 9 C 22 DFF 1 4 0 3 |DIVCLK:10|counter41 (|DIVCLK:10|:11)
- 5 C 22 DFF 1 2 0 5 |DIVCLK:10|counter40 (|DIVCLK:10|:12)
- 8 C 13 DFF 1 3 0 3 |DIVCLK:10|counter32 (|DIVCLK:10|:13)
- 5 C 13 DFF 1 3 0 4 |DIVCLK:10|counter31 (|DIVCLK:10|:14)
- 9 C 13 DFF 1 4 0 4 |DIVCLK:10|counter30 (|DIVCLK:10|:15)
- 2 C 13 DFF 1 4 0 2 |DIVCLK:10|counter25 (|DIVCLK:10|:16)
- 6 C 17 DFF 1 4 0 3 |DIVCLK:10|counter24 (|DIVCLK:10|:17)
- 8 C 15 DFF 1 4 0 3 |DIVCLK:10|counter23 (|DIVCLK:10|:18)
- 5 C 15 DFF 1 4 0 3 |DIVCLK:10|counter22 (|DIVCLK:10|:19)
- 9 C 15 DFF 1 4 0 4 |DIVCLK:10|counter21 (|DIVCLK:10|:20)
- 1 C 15 DFF 1 2 0 5 |DIVCLK:10|counter20 (|DIVCLK:10|:21)
- 7 D 12 DFF 1 4 0 2 |DIVCLK:10|counter112 (|DIVCLK:10|:22)
- 4 D 12 DFF 1 4 0 3 |DIVCLK:10|counter111 (|DIVCLK:10|:23)
- 9 D 12 DFF 1 3 0 4 |DIVCLK:10|counter110 (|DIVCLK:10|:24)
- 6 D 12 DFF 1 3 0 5 |DIVCLK:10|counter19 (|DIVCLK:10|:25)
- 10 D 14 DFF 1 4 0 3 |DIVCLK:10|counter18 (|DIVCLK:10|:26)
- 6 D 14 DFF 1 4 0 4 |DIVCLK:10|counter17 (|DIVCLK:10|:27)
- 9 D 14 DFF 1 2 0 5 |DIVCLK:10|counter16 (|DIVCLK:10|:28)
- 8 D 14 DFF 1 4 0 3 |DIVCLK:10|counter15 (|DIVCLK:10|:29)
- 3 D 14 DFF 1 3 0 4 |DIVCLK:10|counter14 (|DIVCLK:10|:30)
- 6 D 16 DFF 1 3 0 5 |DIVCLK:10|counter13 (|DIVCLK:10|:31)
- 6 D 18 DFF 1 4 0 2 |DIVCLK:10|counter12 (|DIVCLK:10|:32)
- 3 D 18 DFF 1 3 0 3 |DIVCLK:10|counter11 (|DIVCLK:10|:33)
- 7 D 18 DFF 1 1 0 4 |DIVCLK:10|counter10 (|DIVCLK:10|:34)
- 4 D 14 OR2 s 0 3 0 1 |DIVCLK:10|~102~1
- 5 D 14 OR2 s 0 4 0 1 |DIVCLK:10|~102~2
- 3 D 12 OR2 s 0 3 0 1 |DIVCLK:10|~102~3
- 10 C 22 AND2 s 0 3 0 2 |DIVCLK:10|~102~4
- 8 D 12 OR2 ! 0 4 0 18 |DIVCLK:10|:102
- 7 C 15 OR2 s 0 3 0 1 |DIVCLK:10|~153~1
- 2 C 15 OR2 ! 0 4 0 10 |DIVCLK:10|:153
- 6 C 13 OR2 ! 0 3 0 3 |DIVCLK:10|:180
- 6 C 22 OR2 ! 0 3 0 3 |DIVCLK:10|:201
- 4 C 22 AND2 s 0 2 0 3 |DIVCLK:10|~268~1
- 4 C 13 OR2 0 4 0 1 |DIVCLK:10|:351
- 3 C 13 OR2 0 3 0 1 |DIVCLK:10|:357
- 3 C 22 OR2 s 0 4 0 1 |DIVCLK:10|~442~1
- 2 C 22 OR2 s 0 3 0 1 |DIVCLK:10|~448~1
- 7 C 22 AND2 s ! 0 3 0 4 |DIVCLK:10|~454~1
- 3 B 03 OR2 s 1 3 0 2 trafficen~1
- 5 B 05 AND2 0 3 0 2 |TRAFFIC:9|LPM_ADD_SUB:163|addcore:adder|:67
- 10 B 03 OR2 0 2 0 1 |TRAFFIC:9|LPM_ADD_SUB:163|addcore:adder|:83
- 6 D 01 DFF 2 4 1 2 |TRAFFIC:9|:4
- 5 D 01 DFF 2 4 1 1 |TRAFFIC:9|:6
- 4 D 01 DFF 2 4 1 1 |TRAFFIC:9|:8
- 3 D 01 DFF 2 4 1 1 |TRAFFIC:9|:10
- 2 D 01 DFF 2 4 1 2 |TRAFFIC:9|:12
- 6 C 01 DFF 2 4 1 1 |TRAFFIC:9|:14
- 5 C 01 DFF 2 4 1 1 |TRAFFIC:9|:16
- 4 C 01 DFF 2 4 1 2 |TRAFFIC:9|:18
- 3 C 01 DFF 2 4 1 1 |TRAFFIC:9|:20
- 2 C 01 DFF 2 4 1 2 |TRAFFIC:9|:22
- 2 B 01 DFF 2 4 1 1 |TRAFFIC:9|:24
- 3 B 01 DFF 2 4 1 1 |TRAFFIC:9|:26
- 9 B 03 OR2 s 0 4 0 1 |TRAFFIC:9|temp21~1 (|TRAFFIC:9|~30~1)
- 8 B 03 OR2 s 2 2 0 1 |TRAFFIC:9|temp21~2 (|TRAFFIC:9|~30~2)
- 7 B 03 DFF 1 4 0 13 |TRAFFIC:9|temp21 (|TRAFFIC:9|:30)
- 1 B 01 AND2 s 0 1 0 1 |TRAFFIC:9|temp20~1 (|TRAFFIC:9|~31~1)
- 5 B 01 DFF 0 5 0 3 |TRAFFIC:9|temp20 (|TRAFFIC:9|:31)
- 6 B 05 DFF 2 3 0 3 |TRAFFIC:9|temp14 (|TRAFFIC:9|:32)
- 2 B 05 DFF 2 3 0 4 |TRAFFIC:9|temp13 (|TRAFFIC:9|:33)
- 8 B 05 DFF 2 3 0 5 |TRAFFIC:9|temp12 (|TRAFFIC:9|:34)
- 5 B 03 DFF 2 3 0 5 |TRAFFIC:9|temp11 (|TRAFFIC:9|:35)
- 10 B 01 AND2 s ! 2 0 0 1 |TRAFFIC:9|temp10~1 (|TRAFFIC:9|~36~1)
- 4 B 01 DFF 2 3 0 6 |TRAFFIC:9|temp10 (|TRAFFIC:9|:36)
- 2 D 04 OR2 ! 0 2 0 6 |TRAFFIC:9|:178
- 7 B 01 AND2 s 0 1 0 2 |TRAFFIC:9|~188~1
- 6 B 01 OR2 s ! 0 4 0 8 |TRAFFIC:9|~198~1
- 3 B 05 OR2 s 0 3 0 2 |TRAFFIC:9|~208~1
- 8 B 01 OR2 s 0 4 0 10 |TRAFFIC:9|~208~2
- 1 D 01 OR2 ! 0 2 0 5 |TRAFFIC:9|:208
- 10 D 01 OR2 0 4 0 1 |TRAFFIC:9|:344
- 7 D 01 OR2 s 0 3 0 8 |TRAFFIC:9|~403~1
- 8 D 01 OR2 0 4 0 1 |TRAFFIC:9|:413
- 8 C 01 OR2 0 4 0 1 |TRAFFIC:9|:458
- 7 C 01 OR2 0 4 0 1 |TRAFFIC:9|:485
- 4 B 03 OR2 0 3 0 1 |TRAFFIC:9|:611
- 9 D 01 OR2 s 1 3 0 2 |TRAFFIC:9|~668~1
- 6 B 03 AND2 s 1 1 0 3 |TRAFFIC:9|~693~1
- 2 B 03 OR2 s 0 3 0 6 |TRAFFIC:9|~711~1
- 1 D 04 OR2 s 0 3 0 2 |TRAFFIC:9|~711~2
- 9 B 05 OR2 0 4 0 1 |TRAFFIC:9|:735
- 4 B 05 OR2 0 3 0 1 |TRAFFIC:9|:741
- 7 B 05 AND2 s 0 2 0 3 |TRAFFIC:9|~747~1
- 10 B 05 OR2 0 4 0 1 |TRAFFIC:9|:747
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
p = Packed register
Device-Specific Information: c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
traffictrl
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
B: 1/ 96( 1%) 16/ 48( 33%) 0/ 48( 0%) 1/20( 5%) 2/20( 10%) 0/20( 0%)
C: 1/ 96( 1%) 9/ 48( 18%) 7/ 48( 14%) 0/20( 0%) 6/20( 30%) 0/20( 0%)
D: 7/ 96( 7%) 10/ 48( 20%) 4/ 48( 8%) 1/20( 5%) 5/20( 25%) 0/20( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 5/20( 25%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/20( 15%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/20( 10%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
traffictrl
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 26 SYSCLK
DFF 21 |DIVCLK:10|temp4
Device-Specific Information: c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
traffictrl
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 20 RESET
Device-Specific Information: c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
traffictrl
** EQUATIONS **
RESET : INPUT;
SYSCLK : INPUT;
trafficen : INPUT;
-- Node name is 'LED2'
-- Equation name is 'LED2', type is output
LED2 = _LC1_C22;
-- Node name is 'tdata0'
-- Equation name is 'tdata0', type is output
tdata0 = _LC3_B1;
-- Node name is 'tdata1'
-- Equation name is 'tdata1', type is output
tdata1 = _LC2_B1;
-- Node name is 'tdata2'
-- Equation name is 'tdata2', type is output
tdata2 = _LC2_C1;
-- Node name is 'tdata3'
-- Equation name is 'tdata3', type is output
tdata3 = _LC3_C1;
-- Node name is 'tdata4'
-- Equation name is 'tdata4', type is output
tdata4 = _LC4_C1;
-- Node name is 'tdata5'
-- Equation name is 'tdata5', type is output
tdata5 = _LC5_C1;
-- Node name is 'tdata6'
-- Equation name is 'tdata6', type is output
tdata6 = _LC6_C1;
-- Node name is 'tdata7'
-- Equation name is 'tdata7', type is output
tdata7 = _LC2_D1;
-- Node name is 'tdata8'
-- Equation name is 'tdata8', type is output
tdata8 = _LC3_D1;
-- Node name is 'tdata9'
-- Equation name is 'tdata9', type is output
tdata9 = _LC4_D1;
-- Node name is 'tdata10'
-- Equation name is 'tdata10', type is output
tdata10 = _LC5_D1;
-- Node name is 'tdata11'
-- Equation name is 'tdata11', type is output
tdata11 = _LC6_D1;
-- Node name is 'trafficen~1'
-- Equation name is 'trafficen~1', location is LC3_B3, type is buried.
-- synthesized logic cell
_LC3_B3 = LCELL( _EQ001);
_EQ001 = !_LC7_B3 & !_LC8_B1 & trafficen
# _LC2_D4 & trafficen;
-- Node name is '|DIVCLK:10|:34' = '|DIVCLK:10|counter10'
-- Equation name is '_LC7_D18', type is buried
_LC7_D18 = DFF(!_LC7_D18, SYSCLK, VCC, VCC);
-- Node name is '|DIVCLK:10|:33' = '|DIVCLK:10|counter11'
-- Equation name is '_LC3_D18', type is buried
_LC3_D18 = DFF( _EQ002, SYSCLK, VCC, VCC);
_EQ002 = _LC3_D18 & !_LC7_D18 & !_LC8_D12
# !_LC3_D18 & _LC7_D18 & !_LC8_D12;
-- Node name is '|DIVCLK:10|:32' = '|DIVCLK:10|counter12'
-- Equation name is '_LC6_D18', type is buried
_LC6_D18 = DFF( _EQ003, SYSCLK, VCC, VCC);
_EQ003 = !_LC3_D18 & _LC6_D18 & !_LC8_D12
# _LC6_D18 & !_LC7_D18 & !_LC8_D12
# _LC3_D18 & !_LC6_D18 & _LC7_D18 & !_LC8_D12;
-- Node name is '|DIVCLK:10|:31' = '|DIVCLK:10|counter13'
-- Equation name is '_LC6_D16', type is buried
_LC6_D16 = DFF( _EQ004, SYSCLK, VCC, VCC);
_EQ004 = !_LC2_D18 & _LC6_D16 & !_LC8_D12
# _LC2_D18 & !_LC6_D16 & !_LC8_D12;
-- Node name is '|DIVCLK:10|:30' = '|DIVCLK:10|counter14'
-- Equation name is '_LC3_D14', type is buried
_LC3_D14 = DFF( _EQ005, SYSCLK, VCC, VCC);
_EQ005 = _LC3_D14 & !_LC6_D16
# !_LC2_D18 & _LC3_D14
# _LC2_D18 & !_LC3_D14 & _LC6_D16;
-- Node name is '|DIVCLK:10|:29' = '|DIVCLK:10|counter15'
-- Equation name is '_LC8_D14', type is buried
_LC8_D14 = DFF( _EQ006, SYSCLK, VCC, VCC);
_EQ006 = !_LC3_D14 & _LC8_D14
# !_LC6_D16 & _LC8_D14
# !_LC2_D18 & _LC8_D14
# _LC2_D18 & _LC3_D14 & _LC6_D16 & !_LC8_D14;
-- Node name is '|DIVCLK:10|:28' = '|DIVCLK:10|counter16'
-- Equation name is '_LC9_D14', type is buried
_LC9_D14 = DFF( _EQ007, SYSCLK, VCC, VCC);
_EQ007 = !_LC7_D14 & _LC9_D14
# _LC7_D14 & !_LC9_D14;
-- Node name is '|DIVCLK:10|:27' = '|DIVCLK:10|counter17'
-- Equation name is '_LC6_D14', type is buried
_LC6_D14 = DFF( _EQ008, SYSCLK, VCC, VCC);
_EQ008 = _LC6_D14 & !_LC8_D12 & !_LC9_D14
# _LC6_D14 & !_LC7_D14 & !_LC8_D12
# !_LC6_D14 & _LC7_D14 & !_LC8_D12 & _LC9_D14;
-- Node name is '|DIVCLK:10|:26' = '|DIVCLK:10|counter18'
-- Equation name is '_LC10_D14', type is buried
_LC10_D14 = DFF( _EQ009, SYSCLK, VCC, VCC);
_EQ009 = !_LC1_D14 & !_LC8_D12 & _LC10_D14
# !_LC6_D14 & !_LC8_D12 & _LC10_D14
# _LC1_D14 & _LC6_D14 & !_LC8_D12 & !_LC10_D14;
-- Node name is '|DIVCLK:10|:25' = '|DIVCLK:10|counter19'
-- Equation name is '_LC6_D12', type is buried
_LC6_D12 = DFF( _EQ010, SYSCLK, VCC, VCC);
_EQ010 = !_LC2_D14 & _LC6_D12 & !_LC8_D12
# _LC2_D14 & !_LC6_D12 & !_LC8_D12;
-- Node name is '|DIVCLK:10|:21' = '|DIVCLK:10|counter20'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = DFF( _EQ011, SYSCLK, VCC, VCC);
_EQ011 = _LC1_C15 & !_LC8_D12
# !_LC1_C15 & _LC8_D12;
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