traffictrl.rpt

来自「该程序是用VHDL实现的交通灯模拟程序」· RPT 代码 · 共 1,312 行 · 第 1/4 页

-- Equation name is '_LC9_B3', type is buried 
-- synthesized logic cell 
_LC9_B3  = LCELL( _EQ060);
  _EQ060 =  _LC6_B3 & !_LC7_B3 & !_LC8_B1
         #  _LC6_B1 &  _LC6_B3 &  _LC7_B3;

-- Node name is '|TRAFFIC:9|~30~2' = '|TRAFFIC:9|temp21~2' 
-- Equation name is '_LC8_B3', type is buried 
-- synthesized logic cell 
_LC8_B3  = LCELL( _EQ061);
  _EQ061 = !_LC1_D1 &  _LC6_B3
         # !RESET
         # !trafficen;

-- Node name is '|TRAFFIC:9|:30' = '|TRAFFIC:9|temp21' 
-- Equation name is '_LC7_B3', type is buried 
_LC7_B3  = DFF( _EQ062,  _LC1_C22,  VCC,  VCC);
  _EQ062 =  _LC9_B3 &  RESET
         #  _LC7_B3 &  _LC8_B3;

-- Node name is '|TRAFFIC:9|:4' 
-- Equation name is '_LC6_D1', type is buried 
_LC6_D1  = DFF( _EQ063,  _LC1_C22,  RESET,  VCC);
  _EQ063 =  _LC6_D1 & !trafficen
         #  _LC2_B3 &  _LC10_D1;

-- Node name is '|TRAFFIC:9|:6' 
-- Equation name is '_LC5_D1', type is buried 
_LC5_D1  = DFF( _EQ064,  _LC1_C22,  RESET,  VCC);
  _EQ064 =  _LC5_D1 & !trafficen
         #  _LC1_D4 &  _LC5_D1
         #  _LC1_D1 &  _LC1_D4;

-- Node name is '|TRAFFIC:9|:8' 
-- Equation name is '_LC4_D1', type is buried 
_LC4_D1  = DFF( _EQ065,  _LC1_C22,  RESET,  VCC);
  _EQ065 =  _LC3_B3
         #  _LC4_D1 & !trafficen
         #  _LC4_D1 &  _LC7_D1;

-- Node name is '|TRAFFIC:9|:10' 
-- Equation name is '_LC3_D1', type is buried 
_LC3_D1  = DFF( _EQ066,  _LC1_C22,  RESET,  VCC);
  _EQ066 =  _LC2_D4 &  trafficen
         #  _LC3_D1 &  _LC9_D1;

-- Node name is '|TRAFFIC:9|:12' 
-- Equation name is '_LC2_D1', type is buried 
_LC2_D1  = DFF( _EQ067,  _LC1_C22,  RESET,  VCC);
  _EQ067 =  _LC2_D1 & !trafficen
         # !_LC2_D4 &  _LC8_D1 &  trafficen;

-- Node name is '|TRAFFIC:9|:14' 
-- Equation name is '_LC6_C1', type is buried 
_LC6_C1  = DFF( _EQ068,  _LC1_C22,  RESET,  VCC);
  _EQ068 =  _LC6_C1 & !trafficen
         #  _LC2_B3 &  _LC6_C1
         #  _LC2_B3 & !_LC7_D1;

-- Node name is '|TRAFFIC:9|:16' 
-- Equation name is '_LC5_C1', type is buried 
_LC5_C1  = DFF( _EQ069,  _LC1_C22,  RESET,  VCC);
  _EQ069 =  _LC5_C1 &  _LC9_D1
         #  _LC2_D4 &  trafficen;

-- Node name is '|TRAFFIC:9|:18' 
-- Equation name is '_LC4_C1', type is buried 
_LC4_C1  = DFF( _EQ070,  _LC1_C22,  RESET,  VCC);
  _EQ070 =  _LC4_C1 & !trafficen
         # !_LC2_D4 &  _LC8_C1 &  trafficen;

-- Node name is '|TRAFFIC:9|:20' 
-- Equation name is '_LC3_C1', type is buried 
_LC3_C1  = DFF( _EQ071,  _LC1_C22,  RESET,  VCC);
  _EQ071 =  _LC3_C1 & !trafficen
         #  _LC2_B3 &  _LC3_C1
         #  _LC2_B3 & !_LC7_D1;

-- Node name is '|TRAFFIC:9|:22' 
-- Equation name is '_LC2_C1', type is buried 
_LC2_C1  = DFF( _EQ072,  _LC1_C22,  RESET,  VCC);
  _EQ072 =  _LC2_C1 & !trafficen
         #  _LC2_B3 &  _LC7_C1;

-- Node name is '|TRAFFIC:9|:24' 
-- Equation name is '_LC2_B1', type is buried 
_LC2_B1  = DFF( _EQ073,  _LC1_C22,  RESET,  VCC);
  _EQ073 =  _LC2_B1 & !trafficen
         #  _LC1_D4 &  _LC2_B1
         #  _LC1_D1 &  _LC1_D4;

-- Node name is '|TRAFFIC:9|:26' 
-- Equation name is '_LC3_B1', type is buried 
_LC3_B1  = DFF( _EQ074,  _LC1_C22,  RESET,  VCC);
  _EQ074 =  _LC3_B1 & !trafficen
         #  _LC3_B1 &  _LC7_D1
         #  _LC3_B3;

-- Node name is '|TRAFFIC:9|:178' 
-- Equation name is '_LC2_D4', type is buried 
!_LC2_D4 = _LC2_D4~NOT;
_LC2_D4~NOT = LCELL( _EQ075);
  _EQ075 =  _LC7_B3
         # !_LC6_B1;

-- Node name is '|TRAFFIC:9|~188~1' 
-- Equation name is '_LC7_B1', type is buried 
-- synthesized logic cell 
_LC7_B1  = LCELL( _LC8_B1);

-- Node name is '|TRAFFIC:9|~198~1' 
-- Equation name is '_LC6_B1', type is buried 
-- synthesized logic cell 
!_LC6_B1 = _LC6_B1~NOT;
_LC6_B1~NOT = LCELL( _EQ076);
  _EQ076 =  _LC3_B5
         # !_LC4_B1
         #  _LC5_B1
         #  _LC8_B5;

-- Node name is '|TRAFFIC:9|~208~1' 
-- Equation name is '_LC3_B5', type is buried 
-- synthesized logic cell 
_LC3_B5  = LCELL( _EQ077);
  _EQ077 =  _LC5_B3
         #  _LC6_B5
         #  _LC2_B5;

-- Node name is '|TRAFFIC:9|~208~2' 
-- Equation name is '_LC8_B1', type is buried 
-- synthesized logic cell 
_LC8_B1  = LCELL( _EQ078);
  _EQ078 =  _LC4_B1
         # !_LC5_B1
         # !_LC8_B5
         #  _LC3_B5;

-- Node name is '|TRAFFIC:9|:208' 
-- Equation name is '_LC1_D1', type is buried 
!_LC1_D1 = _LC1_D1~NOT;
_LC1_D1~NOT = LCELL( _EQ079);
  _EQ079 = !_LC7_B3
         #  _LC8_B1;

-- Node name is '|TRAFFIC:9|:344' 
-- Equation name is '_LC10_D1', type is buried 
_LC10_D1 = LCELL( _EQ080);
  _EQ080 =  _LC6_D1 & !_LC7_B3
         #  _LC6_D1 &  _LC8_B1
         #  _LC6_B1 &  _LC7_B3;

-- Node name is '|TRAFFIC:9|~403~1' 
-- Equation name is '_LC7_D1', type is buried 
-- synthesized logic cell 
_LC7_D1  = LCELL( _EQ081);
  _EQ081 = !_LC1_D1 & !_LC7_B3
         # !_LC1_D1 & !_LC6_B1;

-- Node name is '|TRAFFIC:9|:413' 
-- Equation name is '_LC8_D1', type is buried 
_LC8_D1  = LCELL( _EQ082);
  _EQ082 =  _LC2_D1 &  _LC7_D1
         # !_LC7_B3 & !_LC8_B1;

-- Node name is '|TRAFFIC:9|:458' 
-- Equation name is '_LC8_C1', type is buried 
_LC8_C1  = LCELL( _EQ083);
  _EQ083 =  _LC4_C1 &  _LC7_D1
         # !_LC7_B3 & !_LC8_B1;

-- Node name is '|TRAFFIC:9|:485' 
-- Equation name is '_LC7_C1', type is buried 
_LC7_C1  = LCELL( _EQ084);
  _EQ084 = !_LC1_D1 &  _LC2_C1
         #  _LC6_B1 &  _LC7_B3;

-- Node name is '|TRAFFIC:9|:611' 
-- Equation name is '_LC4_B3', type is buried 
_LC4_B3  = LCELL( _EQ085);
  _EQ085 =  _LC8_B1 &  _LC10_B3
         #  _LC6_B1;

-- Node name is '|TRAFFIC:9|~668~1' 
-- Equation name is '_LC9_D1', type is buried 
-- synthesized logic cell 
_LC9_D1  = LCELL( _EQ086);
  _EQ086 =  _LC7_B3 &  _LC7_D1
         #  _LC7_D1 &  _LC8_B1
         # !trafficen;

-- Node name is '|TRAFFIC:9|~693~1' 
-- Equation name is '_LC6_B3', type is buried 
-- synthesized logic cell 
_LC6_B3  = LCELL( _EQ087);
  _EQ087 = !_LC2_D4 &  trafficen;

-- Node name is '|TRAFFIC:9|~711~1' 
-- Equation name is '_LC2_B3', type is buried 
-- synthesized logic cell 
_LC2_B3  = LCELL( _EQ088);
  _EQ088 =  _LC6_B3 &  _LC7_B3
         #  _LC6_B3 &  _LC8_B1;

-- Node name is '|TRAFFIC:9|~711~2' 
-- Equation name is '_LC1_D4', type is buried 
-- synthesized logic cell 
_LC1_D4  = LCELL( _EQ089);
  _EQ089 =  _LC2_B3 & !_LC7_B3
         #  _LC2_B3 & !_LC6_B1;

-- Node name is '|TRAFFIC:9|:735' 
-- Equation name is '_LC9_B5', type is buried 
_LC9_B5  = LCELL( _EQ090);
  _EQ090 = !_LC2_B5 &  _LC6_B5 &  _LC7_B5
         # !_LC5_B5 &  _LC6_B5 &  _LC7_B5
         #  _LC2_B5 &  _LC5_B5 & !_LC6_B5 &  _LC7_B5;

-- Node name is '|TRAFFIC:9|:741' 
-- Equation name is '_LC4_B5', type is buried 
_LC4_B5  = LCELL( _EQ091);
  _EQ091 =  _LC2_B5 & !_LC5_B5 &  _LC7_B5
         # !_LC2_B5 &  _LC5_B5 &  _LC7_B5;

-- Node name is '|TRAFFIC:9|~747~1' 
-- Equation name is '_LC7_B5', type is buried 
-- synthesized logic cell 
_LC7_B5  = LCELL( _EQ092);
  _EQ092 =  _LC2_B3 &  _LC7_D1;

-- Node name is '|TRAFFIC:9|:747' 
-- Equation name is '_LC10_B5', type is buried 
_LC10_B5 = LCELL( _EQ093);
  _EQ093 = !_LC5_B3 &  _LC7_B5 &  _LC8_B5
         # !_LC4_B1 &  _LC7_B5 &  _LC8_B5
         #  _LC4_B1 &  _LC5_B3 &  _LC7_B5 & !_LC8_B5;



Project Information           c:\fpga chicago2.0\sample\traffic\traffictrl.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX6000' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:02
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,396K