📄 traffictrl.rpt
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Project Information c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/04/2003 14:09:09
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir LCs
POF Device Pins Pins Pins LCs % Utilized
traffictrl
EPF6016TC144-3 3 13 0 96 7 %
User Pins: 3 13 0
Project Information c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
traffictrl@93 LED2
traffictrl@140 RESET
traffictrl@87 SYSCLK
traffictrl@10 tdata0
traffictrl@11 tdata1
traffictrl@12 tdata2
traffictrl@13 tdata3
traffictrl@14 tdata4
traffictrl@15 tdata5
traffictrl@16 tdata6
traffictrl@21 tdata7
traffictrl@22 tdata8
traffictrl@23 tdata9
traffictrl@24 tdata10
traffictrl@25 tdata11
traffictrl@99 trafficen
Project Information c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
** FILE HIERARCHY **
|traffic:9|
|traffic:9|lpm_add_sub:163|
|traffic:9|lpm_add_sub:163|addcore:adder|
|traffic:9|lpm_add_sub:163|altshift:result_ext_latency_ffs|
|traffic:9|lpm_add_sub:163|altshift:carry_ext_latency_ffs|
|traffic:9|lpm_add_sub:163|altshift:oflow_ext_latency_ffs|
|traffic:9|lpm_add_sub:226|
|traffic:9|lpm_add_sub:226|addcore:adder|
|traffic:9|lpm_add_sub:226|altshift:result_ext_latency_ffs|
|traffic:9|lpm_add_sub:226|altshift:carry_ext_latency_ffs|
|traffic:9|lpm_add_sub:226|altshift:oflow_ext_latency_ffs|
|traffic:9|lpm_add_sub:258|
|traffic:9|lpm_add_sub:258|addcore:adder|
|traffic:9|lpm_add_sub:258|altshift:result_ext_latency_ffs|
|traffic:9|lpm_add_sub:258|altshift:carry_ext_latency_ffs|
|traffic:9|lpm_add_sub:258|altshift:oflow_ext_latency_ffs|
|traffic:9|lpm_add_sub:290|
|traffic:9|lpm_add_sub:290|addcore:adder|
|traffic:9|lpm_add_sub:290|altshift:result_ext_latency_ffs|
|traffic:9|lpm_add_sub:290|altshift:carry_ext_latency_ffs|
|traffic:9|lpm_add_sub:290|altshift:oflow_ext_latency_ffs|
|divclk:10|
|divclk:10|lpm_add_sub:88|
|divclk:10|lpm_add_sub:88|addcore:adder|
|divclk:10|lpm_add_sub:88|altshift:result_ext_latency_ffs|
|divclk:10|lpm_add_sub:88|altshift:carry_ext_latency_ffs|
|divclk:10|lpm_add_sub:88|altshift:oflow_ext_latency_ffs|
|divclk:10|lpm_add_sub:146|
|divclk:10|lpm_add_sub:146|addcore:adder|
|divclk:10|lpm_add_sub:146|altshift:result_ext_latency_ffs|
|divclk:10|lpm_add_sub:146|altshift:carry_ext_latency_ffs|
|divclk:10|lpm_add_sub:146|altshift:oflow_ext_latency_ffs|
|divclk:10|lpm_add_sub:176|
|divclk:10|lpm_add_sub:176|addcore:adder|
|divclk:10|lpm_add_sub:176|altshift:result_ext_latency_ffs|
|divclk:10|lpm_add_sub:176|altshift:carry_ext_latency_ffs|
|divclk:10|lpm_add_sub:176|altshift:oflow_ext_latency_ffs|
|divclk:10|lpm_add_sub:197|
|divclk:10|lpm_add_sub:197|addcore:adder|
|divclk:10|lpm_add_sub:197|altshift:result_ext_latency_ffs|
|divclk:10|lpm_add_sub:197|altshift:carry_ext_latency_ffs|
|divclk:10|lpm_add_sub:197|altshift:oflow_ext_latency_ffs|
Device-Specific Information: c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
traffictrl
***** Logic for device 'traffictrl' compiled without errors.
Device: EPF6016TC144-3
FLEX 6000 Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
Enable JTAG Support = OFF
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S S ^ S S S S S S S S S S S S S S S S
E E E E R E E E E E E E E E E E ^ V D E E E E E E E E E E E E E E E E
R R R R E R R R R R R R R R R R D C A R R R R R R R R R R R R R R R R
V V V V S V V V V V V V V V V V C C G T V V V V V V V V V V V V V V V V
E E E E E E E E E E E E E E E E L I N A E E E E E E E E E E E E E E E E
D D D D T D D D D D D D D D D D K O D 0 D D D D D D D D D D D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
RESERVED | 1 108 | RESERVED
RESERVED | 2 107 | RESERVED
RESERVED | 3 106 | RESERVED
^nCE | 4 105 | ^CONF_DONE
GND | 5 104 | VCCIO
VCCINT | 6 103 | VCCINT
VCCIO | 7 102 | GND
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
tdata0 | 10 99 | trafficen
tdata1 | 11 98 | RESERVED
tdata2 | 12 97 | RESERVED
&tdata3 | 13 96 | RESERVED
tdata4 | 14 95 | RESERVED
tdata5 | 15 94 | RESERVED
tdata6 | 16 93 | LED2
GND | 17 92 | GND
GND | 18 91 | VCCIO
VCCIO | 19 EPF6016TC144-3 90 | GND
GND | 20 89 | GND
tdata7 | 21 88 | RESERVED
tdata8 | 22 87 | SYSCLK
tdata9 | 23 86 | RESERVED
tdata10 | 24 85 | RESERVED
tdata11 | 25 84 | RESERVED
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
GND | 30 79 | RESERVED
VCCINT | 31 78 | VCCIO
VCCIO | 32 77 | VCCINT
^MSEL | 33 76 | GND
RESERVED | 34 75 | RESERVED
RESERVED | 35 74 | RESERVED
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R R R R R R R R R R R R R R ^ G V ^ R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E n N C n E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S S S C D C S S S S S S S S S S S S S S S S S
E E E E E E E E E E E E E E E E O I T E E E E E E E E E E E E E E E E
R R R R R R R R R R R R R R R R N O A R R R R R R R R R R R R R R R R
V V V V V V V V V V V V V V V V F T V V V V V V V V V V V V V V V V
E E E E E E E E E E E E E E E E I U E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D G S D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
traffictrl
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Sync. Sync. Left External Right External Borrowed LC1
Block Logic Cells Driven Driven Clocks Clears Clear Load Interconnect Interconnect Inputs
B1 9/10( 90%) 2/10( 20%) 0/10( 0%) 1/2 1/2 0/1 0/1 4/22( 18%) 7/22( 31%) 2/4
B3 9/10( 90%) 3/10( 30%) 0/10( 0%) 1/2 0/2 0/1 0/1 3/22( 13%) 7/22( 31%) 1/4
B5 9/10( 90%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 3/22( 13%) 7/22( 31%) 1/4
C1 7/10( 70%) 0/10( 0%) 0/10( 0%) 1/2 1/2 0/1 0/1 5/22( 22%) 8/22( 36%) 2/4
C13 8/10( 80%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 4/22( 18%) 1/4
C15 9/10( 90%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 3/22( 13%) 1/4
C17 1/10( 10%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 3/22( 13%) 1/4
C22 10/10(100%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 3/22( 13%) 1/4
D1 10/10(100%) 2/10( 20%) 0/10( 0%) 1/2 1/2 0/1 0/1 5/22( 22%) 9/22( 40%) 2/4
D4 2/10( 20%) 2/10( 20%) 0/10( 0%) 0/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4
D12 7/10( 70%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 4/22( 18%) 1/4
D14 10/10(100%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 5/22( 22%) 1/4
D16 1/10( 10%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 0/22( 0%) 3/22( 13%) 1/4
D18 4/10( 40%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 0/22( 0%) 2/22( 9%) 1/4
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 16/113 ( 14%)
Total logic cells used: 96/1320 ( 7%)
Average fan-in: 3.33/4 ( 83%)
Total fan-in: 320/5280 ( 6%)
Total input pins required: 3
Total output pins required: 13
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 96
Total flipflops required: 45
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Synthesized logic cells: 24/1320 ( 1%)
Logic Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 Total
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B: 9 0 9 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27
C: 7 0 0 0 0 0 0 0 0 0 0 0 8 0 9 0 1 0 0 0 0 10 35
D: 10 0 0 2 0 0 0 0 0 0 0 7 0 10 0 1 0 4 0 0 0 0 34
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Total: 26 0 9 2 9 0 0 0 0 0 0 7 8 10 9 1 1 4 0 0 0 10 96
Device-Specific Information: c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
traffictrl
** INPUTS **
Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
140 - - 01 INPUT 0 0 0 20 RESET
87 - D -- INPUT 0 0 0 26 SYSCLK
99 - B -- INPUT 0 0 0 22 trafficen
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
Device-Specific Information: c:\fpga chicago2.0\sample\traffic\traffictrl.rpt
traffictrl
** OUTPUTS **
Fed By Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
93 - C -- OUTPUT $ 0 1 0 0 LED2
10 - B -- OUTPUT $ 0 1 0 0 tdata0
11 - B -- OUTPUT $ 0 1 0 0 tdata1
12 - C -- OUTPUT $ 0 1 0 0 tdata2
13 - C -- OUTPUT $ 0 1 0 0 tdata3
14 - C -- OUTPUT $ 0 1 0 0 tdata4
15 - C -- OUTPUT $ 0 1 0 0 tdata5
16 - C -- OUTPUT $ 0 1 0 0 tdata6
21 - D -- OUTPUT $ 0 1 0 0 tdata7
22 - D -- OUTPUT $ 0 1 0 0 tdata8
23 - D -- OUTPUT $ 0 1 0 0 tdata9
24 - D -- OUTPUT $ 0 1 0 0 tdata10
25 - D -- OUTPUT $ 0 1 0 0 tdata11
Code:
s = Synthesized pin or logic cell
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