decode.vhd

该程序是用VHDL语言实现的时钟程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY decode IS
	PORT(	selsl	:	IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			selsh	:	IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			selml	:	IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			selmh	:	IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			selhl	:	IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			selhh	:	IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			disable	:	IN	STD_LOGIC_VECTOR(5 DOWNTO 0);
			qsl		:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
			qsh		:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
			qml		:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
			qmh		:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
			qhl		:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
			qhh		:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
END decode;

ARCHITECTURE func1 OF decode IS
	COMPONENT deco10 IS
   	PORT (	sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      		disable : IN STD_LOGIC;
      		q   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
	END COMPONENT;
BEGIN
	mydecode1: deco10 PORT MAP(sel => selsl,disable => disable(0),q => qsl);
	mydecode2: deco10 PORT MAP(sel => selsh,disable => disable(1),q => qsh);
	mydecode3: deco10 PORT MAP(sel => selml,disable => disable(2),q => qml);
	mydecode4: deco10 PORT MAP(sel => selmh,disable => disable(3),q => qmh);
	mydecode5: deco10 PORT MAP(sel => selhl,disable => disable(4),q => qhl);
	mydecode6: deco10 PORT MAP(sel => selhh,disable => disable(5),q => qhh);
END func1;