📄 time.rpt
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- 3 F 03 OR2 0 4 0 1 |TIMEC:91|:602
- 2 F 11 OR2 s 0 3 0 1 |TIMEC:91|~604~1
- 1 E 01 OR2 0 4 0 1 |TIMEC:91|:605
- 2 E 01 OR2 0 4 0 1 |TIMEC:91|:608
- 3 B 18 OR2 0 4 0 1 |TIMEC:91|:612
- 4 B 03 OR2 0 4 0 1 |TIMEC:91|:616
- 6 F 03 OR2 0 4 0 1 |TIMEC:91|:623
- 6 E 09 OR2 0 4 0 1 |TIMEC:91|:626
- 1 E 09 OR2 0 4 0 1 |TIMEC:91|:629
- 1 B 18 OR2 0 4 0 1 |TIMEC:91|:633
- 6 B 03 OR2 0 4 0 1 |TIMEC:91|:637
- 1 F 06 OR2 0 4 0 1 |TIMEC:91|:645
- 7 E 02 OR2 s 0 4 0 7 |TIMEC:91|~648~1
- 2 F 06 OR2 0 4 0 1 |TIMEC:91|:649
- 6 E 02 OR2 s 0 4 0 7 |TIMEC:91|~651~1
- 4 E 01 OR2 0 4 0 1 |TIMEC:91|:652
- 2 E 02 OR2 s 0 4 0 7 |TIMEC:91|~654~1
- 3 E 01 OR2 0 4 0 1 |TIMEC:91|:655
- 4 E 02 OR2 s 0 4 0 7 |TIMEC:91|~657~1
- 5 B 03 OR2 0 4 0 1 |TIMEC:91|:658
- 2 A 15 OR2 1 3 1 0 |TIMEC:91|:678
- 2 B 11 OR2 1 3 1 0 |TIMEC:91|:684
- 3 A 03 OR2 1 3 1 0 |TIMEC:91|:690
- 1 A 03 OR2 1 3 1 0 |TIMEC:91|:696
- 2 A 03 OR2 1 3 1 0 |TIMEC:91|:702
- 1 B 03 OR2 1 3 1 0 |TIMEC:91|:708
- 3 B 03 OR2 1 3 1 0 |TIMEC:91|:714
- 2 B 03 OR2 1 3 1 0 |TIMEC:91|:720
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
p = Packed register
Device-Specific Information:d:\wang\chicago1.0&2.0\sample\chicago2.0\time\time.rpt
time
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 22/ 96( 22%) 23/ 48( 47%) 13/ 48( 27%) 2/20( 10%) 0/20( 0%) 0/20( 0%)
B: 11/ 96( 11%) 16/ 48( 33%) 4/ 48( 8%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
C: 6/ 96( 6%) 20/ 48( 41%) 2/ 48( 4%) 1/20( 5%) 1/20( 5%) 0/20( 0%)
D: 6/ 96( 6%) 1/ 48( 2%) 8/ 48( 16%) 1/20( 5%) 1/20( 5%) 0/20( 0%)
E: 11/ 96( 11%) 23/ 48( 47%) 1/ 48( 2%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
F: 16/ 96( 16%) 9/ 48( 18%) 3/ 48( 6%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 5/20( 25%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 8/20( 40%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 8/20( 40%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 5/20( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 5/20( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 5/20( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 5/20( 25%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
08: 5/20( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 4/20( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 4/20( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 6/20( 30%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/20( 10%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 6/20( 30%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 4/20( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/20( 5%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/20( 5%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/20( 5%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/20( 10%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\wang\chicago1.0&2.0\sample\chicago2.0\time\time.rpt
time
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 31 CLK
LCELL 21 |CNT:81|:1654
DFF 11 |DIVCLK:71|temp1
DFF 9 |DIVCLK:71|temp2
DFF 5 |SYSCTRL:90|tmpsel
DFF 3 |DIVCLK:71|temp3
Device-Specific Information:d:\wang\chicago1.0&2.0\sample\chicago2.0\time\time.rpt
time
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 42 RST
DFF 13 |SYSCTRL:90|tmpset
LCELL 5 |SYSCTRL:90|:582
Device-Specific Information:d:\wang\chicago1.0&2.0\sample\chicago2.0\time\time.rpt
time
** EQUATIONS **
ADJ : INPUT;
CLK : INPUT;
RST : INPUT;
SEL : INPUT;
SET : INPUT;
-- Node name is 'comm0'
-- Equation name is 'comm0', type is output
comm0 = _LC9_A15;
-- Node name is 'comm1'
-- Equation name is 'comm1', type is output
comm1 = _LC8_A15;
-- Node name is 'comm2'
-- Equation name is 'comm2', type is output
comm2 = _LC7_A15;
-- Node name is 'comm3'
-- Equation name is 'comm3', type is output
comm3 = _LC1_A15;
-- Node name is 'comm4'
-- Equation name is 'comm4', type is output
comm4 = _LC6_A15;
-- Node name is 'comm5'
-- Equation name is 'comm5', type is output
comm5 = _LC3_A15;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC2_B3;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC3_B3;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC1_B3;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC2_A3;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC1_A3;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC3_A3;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC2_B11;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = _LC2_A15;
-- Node name is 'LED1'
-- Equation name is 'LED1', type is output
LED1 = _LC6_D22;
-- Node name is 'LED2'
-- Equation name is 'LED2', type is output
LED2 = _LC6_C22;
-- Node name is '|CNT:81|LPM_ADD_SUB:630|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = LCELL( _EQ001);
_EQ001 = _LC2_C10 & _LC6_C10;
-- Node name is '|CNT:81|LPM_ADD_SUB:630|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC10_C10', type is buried
_LC10_C10 = LCELL( _EQ002);
_EQ002 = _LC3_B1 & _LC3_C10;
-- Node name is '|CNT:81|LPM_ADD_SUB:809|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ003);
_EQ003 = _LC2_C4 & _LC3_C4;
-- Node name is '|CNT:81|LPM_ADD_SUB:809|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C4', type is buried
_LC5_C4 = LCELL( _EQ004);
_EQ004 = _LC2_C4 & _LC3_C4 & _LC6_C4;
-- Node name is '|CNT:81|LPM_ADD_SUB:1008|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A7', type is buried
_LC6_A7 = LCELL( _EQ005);
_EQ005 = _LC3_A7 & _LC7_A7;
-- Node name is '|CNT:81|LPM_ADD_SUB:1008|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A7', type is buried
_LC2_A7 = LCELL( _EQ006);
_EQ006 = _LC3_A7 & _LC4_A7 & _LC7_A7;
-- Node name is '|CNT:81|LPM_ADD_SUB:1227|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = LCELL( _EQ007);
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