📄 time.rpt
字号:
^MSEL | 33 76 | GND
RESERVED | 34 75 | RESERVED
RESERVED | 35 74 | RESERVED
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R R R R R R R R R R R R R R ^ G V ^ R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E n N C n E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S S S C D C S S S S S S S S S S S S S S S S S
E E E E E E E E E E E E E E E E O I T E E E E E E E E E E E E E E E E
R R R R R R R R R R R R R R R R N O A R R R R R R R R R R R R R R R R
V V V V V V V V V V V V V V V V F T V V V V V V V V V V V V V V V V
E E E E E E E E E E E E E E E E I U E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D G S D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:d:\wang\chicago1.0&2.0\sample\chicago2.0\time\time.rpt
time
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Sync. Sync. Left External Right External Borrowed LC1
Block Logic Cells Driven Driven Clocks Clears Clear Load Interconnect Interconnect Inputs
A1 1/10( 10%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4
A3 7/10( 70%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 10/22( 45%) 11/22( 50%) 0/4
A5 10/10(100%) 5/10( 50%) 0/10( 0%) 1/2 1/2 0/1 0/1 4/22( 18%) 5/22( 22%) 2/4
A7 8/10( 80%) 4/10( 40%) 0/10( 0%) 1/2 1/2 0/1 0/1 2/22( 9%) 3/22( 13%) 2/4
A9 1/10( 10%) 1/10( 10%) 0/10( 0%) 1/2 1/2 0/1 0/1 1/22( 4%) 2/22( 9%) 2/4
A11 1/10( 10%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4
A13 5/10( 50%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 8/22( 36%) 8/22( 36%) 0/4
A15 9/10( 90%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 3/22( 13%) 6/22( 27%) 1/4
A16 1/10( 10%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 1/22( 4%) 0/4
A17 3/10( 30%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 5/22( 22%) 4/22( 18%) 0/4
A18 1/10( 10%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4
A21 1/10( 10%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4
B1 4/10( 40%) 2/10( 20%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4
B3 9/10( 90%) 3/10( 30%) 0/10( 0%) 0/2 0/2 0/1 0/1 9/22( 40%) 12/22( 54%) 0/4
B7 4/10( 40%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 0/22( 0%) 2/22( 9%) 1/4
B8 1/10( 10%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4
B9 10/10(100%) 2/10( 20%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 8/22( 36%) 0/4
B11 3/10( 30%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 3/22( 13%) 4/22( 18%) 0/4
B15 5/10( 50%) 4/10( 40%) 0/10( 0%) 1/2 0/2 0/1 0/1 0/22( 0%) 4/22( 18%) 1/4
B18 10/10(100%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 4/22( 18%) 6/22( 27%) 0/4
B20 2/10( 20%) 2/10( 20%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4
C1 1/10( 10%) 0/10( 0%) 0/10( 0%) 1/2 1/2 0/1 0/1 1/22( 4%) 2/22( 9%) 2/4
C3 1/10( 10%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 0/22( 0%) 2/22( 9%) 0/4
C4 10/10(100%) 5/10( 50%) 0/10( 0%) 1/2 1/2 0/1 0/1 4/22( 18%) 4/22( 18%) 2/4
C8 10/10(100%) 4/10( 40%) 0/10( 0%) 1/2 1/2 0/1 0/1 3/22( 13%) 4/22( 18%) 2/4
C10 8/10( 80%) 4/10( 40%) 0/10( 0%) 1/2 1/2 0/1 0/1 3/22( 13%) 4/22( 18%) 2/4
C11 3/10( 30%) 2/10( 20%) 0/10( 0%) 0/2 0/2 0/1 0/1 1/22( 4%) 3/22( 13%) 0/4
C14 6/10( 60%) 6/10( 60%) 0/10( 0%) 1/2 1/2 0/1 0/1 1/22( 4%) 1/22( 4%) 2/4
C17 1/10( 10%) 1/10( 10%) 0/10( 0%) 1/2 1/2 0/1 0/1 1/22( 4%) 2/22( 9%) 2/4
C22 2/10( 20%) 0/10( 0%) 0/10( 0%) 2/2 0/2 0/1 0/1 0/22( 0%) 5/22( 22%) 2/4
D3 8/10( 80%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 3/22( 13%) 2/22( 9%) 1/4
D9 6/10( 60%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 3/22( 13%) 1/4
D11 1/10( 10%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4
D12 1/10( 10%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 1/4
D13 9/10( 90%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 5/22( 22%) 2/22( 9%) 1/4
D17 10/10(100%) 0/10( 0%) 0/10( 0%) 1/2 0/2 0/1 0/1 1/22( 4%) 5/22( 22%) 1/4
D19 5/10( 50%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 4/22( 18%) 1/4
D22 8/10( 80%) 1/10( 10%) 0/10( 0%) 1/2 0/2 0/1 0/1 2/22( 9%) 3/22( 13%) 1/4
E1 8/10( 80%) 2/10( 20%) 0/10( 0%) 0/2 0/2 0/1 0/1 8/22( 36%) 7/22( 31%) 0/4
E2 10/10(100%) 8/10( 80%) 0/10( 0%) 2/2 1/2 0/1 0/1 9/22( 40%) 7/22( 31%) 3/4
E6 2/10( 20%) 2/10( 20%) 0/10( 0%) 1/2 0/2 0/1 0/1 0/22( 0%) 2/22( 9%) 1/4
E7 9/10( 90%) 0/10( 0%) 0/10( 0%) 1/2 1/2 0/1 0/1 1/22( 4%) 2/22( 9%) 2/4
E9 4/10( 40%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 6/22( 27%) 7/22( 31%) 0/4
E10 1/10( 10%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4
E12 6/10( 60%) 2/10( 20%) 0/10( 0%) 0/2 0/2 0/1 0/1 9/22( 40%) 6/22( 27%) 0/4
F1 1/10( 10%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4
F3 9/10( 90%) 3/10( 30%) 0/10( 0%) 0/2 0/2 0/1 0/1 8/22( 36%) 8/22( 36%) 0/4
F6 9/10( 90%) 3/10( 30%) 0/10( 0%) 0/2 0/2 0/1 0/1 9/22( 40%) 6/22( 27%) 0/4
F8 1/10( 10%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 1/22( 4%) 2/22( 9%) 0/4
F9 1/10( 10%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4
F10 1/10( 10%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 1/22( 4%) 0/22( 0%) 0/4
F11 7/10( 70%) 1/10( 10%) 0/10( 0%) 0/2 0/2 0/1 0/1 6/22( 27%) 4/22( 18%) 0/4
F13 1/10( 10%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 1/22( 4%) 0/4
F16 8/10( 80%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 4/22( 18%) 3/22( 13%) 0/4
F18 3/10( 30%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 2/22( 9%) 0/4
F21 1/10( 10%) 0/10( 0%) 0/10( 0%) 0/2 0/2 0/1 0/1 2/22( 9%) 0/22( 0%) 0/4
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 21/113 ( 18%)
Total logic cells used: 268/1320 ( 20%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 904/5280 ( 17%)
Total input pins required: 5
Total output pins required: 16
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 268
Total flipflops required: 76
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Synthesized logic cells: 42/1320 ( 3%)
Logic Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 Total
A: 1 0 7 0 10 0 8 0 1 0 1 0 5 0 9 1 3 1 0 0 1 0 48
B: 4 0 9 0 0 0 4 1 10 0 3 0 0 0 5 0 0 10 0 2 0 0 48
C: 1 0 1 10 0 0 0 10 0 8 3 0 0 6 0 0 1 0 0 0 0 2 42
D: 0 0 8 0 0 0 0 0 6 0 1 1 9 0 0 0 10 0 5 0 0 8 48
E: 8 10 0 0 0 2 9 0 4 1 0 6 0 0 0 0 0 0 0 0 0 0 40
F: 1 0 9 0 0 9 0 1 1 1 7 0 1 0 0 8 0 3 0 0 1 0 42
Total: 15 10 34 10 10 11 21 12 22 10 15 7 15 6 14 9 14 14 5 2 2 10 268
Device-Specific Information:d:\wang\chicago1.0&2.0\sample\chicago2.0\time\time.rpt
time
** INPUTS **
Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
142 - A -- INPUT 0 0 0 1 ADJ
87 - D -- INPUT 0 0 0 31 CLK
140 - - 01 INPUT 0 0 0 42 RST
141 - A -- INPUT 0 0 0 1 SEL
95 - C -- INPUT 0 0 0 1 SET
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
Device-Specific Information:d:\wang\chicago1.0&2.0\sample\chicago2.0\time\time.rpt
time
** OUTPUTS **
Fed By Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
122 - - 14 OUTPUT $ 0 1 0 0 comm0
121 - - 15 OUTPUT $ 0 1 0 0 comm1
119 - - 17 OUTPUT 0 1 0 0 comm2
118 - - 18 OUTPUT 0 1 0 0 comm3
116 - - 19 OUTPUT 0 1 0 0 comm4
115 - - 20 OUTPUT 0 1 0 0 comm5
138 - - 03 OUTPUT 0 1 0 0 data0
137 - - 04 OUTPUT 0 1 0 0 data1
136 - - 05 OUTPUT 0 1 0 0 data2
135 - - 06 OUTPUT 0 1 0 0 data3
131 - - 09 OUTPUT 0 1 0 0 data4
132 - - 08 OUTPUT 0 1 0 0 data5
133 - - 07 OUTPUT 0 1 0 0 data6
134 - - 07 OUTPUT 0 1 0 0 data7
88 - D -- OUTPUT $ 0 1 0 0 LED1
93 - C -- OUTPUT $ 0 1 0 0 LED2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
Device-Specific Information:d:\wang\chicago1.0&2.0\sample\chicago2.0\time\time.rpt
time
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC Row Col Primitive Code INP FBK OUT FBK Name
- 3 B 01 AND2 0 2 0 3 |CNT:81|LPM_ADD_SUB:630|addcore:adder|:59
- 10 C 10 AND2 0 2 0 1 |CNT:81|LPM_ADD_SUB:630|addcore:adder|:63
- 1 C 04 AND2 0 2 0 1 |CNT:81|LPM_ADD_SUB:809|addcore:adder|:59
- 5 C 04 AND2 0 3 0 1 |CNT:81|LPM_ADD_SUB:809|addcore:adder|:63
- 6 A 07 AND2 0 2 0 1 |CNT:81|LPM_ADD_SUB:1008|addcore:adder|:59
- 2 A 07 AND2 0 3 0 1 |CNT:81|LPM_ADD_SUB:1008|addcore:adder|:63
- 1 A 05 AND2 0 2 0 1 |CNT:81|LPM_ADD_SUB:1227|addcore:adder|:59
- 4 A 05 AND2 0 3 0 1 |CNT:81|LPM_ADD_SUB:1227|addcore:adder|:63
- 1 C 08 OR2 ! 0 2 0 5 |CNT:81|LPM_ADD_SUB:1480|addcore:adder|:63
- 5 C 08 AND2 0 2 0 1 |CNT:81|LPM_ADD_SUB:1480|addcore:adder|:67
- 4 C 08 AND2 0 3 0 1 |CNT:81|LPM_ADD_SUB:1480|addcore:adder|:71
- 9 C 10 DFF 1 5 0 14 |CNT:81|tqsl3 (|CNT:81|:33)
- 3 C 10 DFF 1 5 0 15 |CNT:81|tqsl2 (|CNT:81|:34)
- 6 C 10 DFF 1 5 0 14 |CNT:81|tqsl1 (|CNT:81|:35)
- 2 C 10 DFF 1 4 0 14 |CNT:81|tqsl0 (|CNT:81|:36)
- 8 A 07 DFF 1 5 0 9 |CNT:81|tqml3 (|CNT:81|:37)
- 4 A 07 DFF 1 5 0 10 |CNT:81|tqml2 (|CNT:81|:38)
- 7 A 07 DFF 1 5 0 11 |CNT:81|tqml1 (|CNT:81|:39)
- 3 A 07 DFF 1 4 0 12 |CNT:81|tqml0 (|CNT:81|:40)
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