timec.vhd

来自「该程序是用VHDL语言实现的时钟程序」· VHDL 代码 · 共 45 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY timec IS
	PORT(	clk:    IN  STD_LOGIC;
	
			q:		OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)
		 );
END timec;

ARCHITECTURE rtl OF timec IS
signal cnt:integer range 0 to 1000;
SIGNAL tq : STD_LOGIC_VECTOR(7 DOWNTO 0);
--BEGIN
--  PROCESS(clk)
 
 
  begin
    --if(clk'event and clk='1')then
       
    --   cnt:=cnt+1;
     --  if(cnt1>MAX1)then
     --   cnt1:=0;
     --  end if;
   
    WITH cnt SELECT
	tq<="00111111" WHEN 0,
		"00000110" WHEN 1,
		"01011011" WHEN 2,
		"01001111" WHEN 3,
		"01100110" WHEN 4,
		"01101101" WHEN 5,
		"01111101" WHEN 6,
		"00100111" WHEN 7,
		"01111111" WHEN 8,
		"01101111" WHEN 9,
		"00000000" WHEN OTHERS;
	q <= tq;
	
	--end if;
  --END PROCESS;
                                                                                      
	
END rtl;