system.h

这是一个基于FPGA/SOPC设计的简单串口程序

/* system.h
 *
 * Machine generated for a CPU named "cpu_0" as defined in:
 * D:\de2.1\software\hello_world_0_syslib\..\..\nios_system.ptf
 *
 * Generated: 2009-05-10 21:31:08.968
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME ""
#define ALT_CPU_NAME "cpu_0"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEII"
#define ALT_STDIN "/dev/uart_0"
#define ALT_STDIN_TYPE "altera_avalon_uart"
#define ALT_STDIN_BASE 0x00008800
#define ALT_STDIN_DEV uart_0
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/uart_0"
#define ALT_STDOUT_TYPE "altera_avalon_uart"
#define ALT_STDOUT_BASE 0x00008800
#define ALT_STDOUT_DEV uart_0
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/uart_0"
#define ALT_STDERR_TYPE "altera_avalon_uart"
#define ALT_STDERR_BASE 0x00008800
#define ALT_STDERR_DEV uart_0
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00000020
#define NIOS2_RESET_ADDR 0x00000000
#define NIOS2_BREAK_ADDR 0x00008020

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_TIMER

/*
 * uart_0 configuration
 *
 */

#define UART_0_NAME "/dev/uart_0"
#define UART_0_TYPE "altera_avalon_uart"
#define UART_0_BASE 0x00008800
#define UART_0_SPAN 32
#define UART_0_IRQ 0
#define UART_0_BAUD 115200
#define UART_0_DATA_BITS 8
#define UART_0_FIXED_BAUD 1
#define UART_0_PARITY 'N'
#define UART_0_STOP_BITS 1
#define UART_0_USE_CTS_RTS 0
#define UART_0_USE_EOP_REGISTER 0
#define UART_0_SIM_TRUE_BAUD 0
#define UART_0_SIM_CHAR_STREAM ""
#define UART_0_FREQ 50000000
#define ALT_MODULE_CLASS_uart_0 altera_avalon_uart

/*
 * onchip_memory_0 configuration
 *
 */

#define ONCHIP_MEMORY_0_NAME "/dev/onchip_memory_0"
#define ONCHIP_MEMORY_0_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEMORY_0_BASE 0x00000000
#define ONCHIP_MEMORY_0_SPAN 32768
#define ONCHIP_MEMORY_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY_0_RAM_BLOCK_TYPE "M4K"
#define ONCHIP_MEMORY_0_INIT_CONTENTS_FILE "onchip_memory_0"
#define ONCHIP_MEMORY_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEMORY_0_GUI_RAM_BLOCK_TYPE "Automatic"
#define ONCHIP_MEMORY_0_WRITEABLE 1
#define ONCHIP_MEMORY_0_DUAL_PORT 0
#define ONCHIP_MEMORY_0_SIZE_VALUE 32
#define ONCHIP_MEMORY_0_SIZE_MULTIPLE 1024
#define ONCHIP_MEMORY_0_CONTENTS_INFO "SIMDIR/onchip_memory_0.dat 1241961760 QUARTUS_PROJECT_DIR/onchip_memory_0.hex 1241961760"
#define ALT_MODULE_CLASS_onchip_memory_0 altera_avalon_onchip_memory2

/*
 * timer_0 configuration
 *
 */

#define TIMER_0_NAME "/dev/timer_0"
#define TIMER_0_TYPE "altera_avalon_timer"
#define TIMER_0_BASE 0x00008820
#define TIMER_0_SPAN 32
#define TIMER_0_IRQ 1
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_SNAPSHOT 1
#define TIMER_0_PERIOD 500
#define TIMER_0_PERIOD_UNITS "ms"
#define TIMER_0_RESET_OUTPUT 0
#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_0_MULT 0.001
#define TIMER_0_FREQ 50000000
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK TIMER_0
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       ONCHIP_MEMORY_0
#define ALT_RODATA_DEVICE     ONCHIP_MEMORY_0
#define ALT_RWDATA_DEVICE     ONCHIP_MEMORY_0
#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY_0
#define ALT_RESET_DEVICE      ONCHIP_MEMORY_0

/*
 * The text section is initialised so no bootloader will be required.
 * Set a variable to tell crt0.S to provide code at the reset address and
 * to initialise rwdata if appropriate.
 */

#define ALT_NO_BOOTLOADER


#endif /* __SYSTEM_H_ */