controlb.tan.rpt

vhdl语言编写的交通灯程序

; N/A   ; None         ; 11.231 ns  ; temp_l[2] ; timel[2] ; clk        ;
; N/A   ; None         ; 11.179 ns  ; tempr     ; r        ; clk        ;
; N/A   ; None         ; 9.763 ns   ; temp_h[3] ; timeh[3] ; clk        ;
; N/A   ; None         ; 9.759 ns   ; temp_h[2] ; timeh[2] ; clk        ;
; N/A   ; None         ; 9.723 ns   ; temp_l[1] ; timel[1] ; clk        ;
; N/A   ; None         ; 9.695 ns   ; tempg     ; g        ; clk        ;
; N/A   ; None         ; 9.688 ns   ; tempy     ; y        ; clk        ;
; N/A   ; None         ; 9.639 ns   ; temp_l[0] ; timel[0] ; clk        ;
; N/A   ; None         ; 9.583 ns   ; temp_h[0] ; timeh[0] ; clk        ;
; N/A   ; None         ; 9.552 ns   ; temp_h[1] ; timeh[1] ; clk        ;
; N/A   ; None         ; 9.505 ns   ; tempt     ; t        ; clk        ;
; N/A   ; None         ; 9.496 ns   ; temp_l[3] ; timel[3] ; clk        ;
+-------+--------------+------------+-----------+----------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; -4.433 ns ; show ; temp_h[0]         ; clk      ;
; N/A           ; None        ; -4.435 ns ; show ; temp_h[1]         ; clk      ;
; N/A           ; None        ; -4.479 ns ; show ; temp_color.turn   ; clk      ;
; N/A           ; None        ; -4.480 ns ; show ; temp_l[3]         ; clk      ;
; N/A           ; None        ; -4.483 ns ; show ; temp_color.green  ; clk      ;
; N/A           ; None        ; -4.483 ns ; show ; temp_color.yellow ; clk      ;
; N/A           ; None        ; -4.523 ns ; show ; tempy             ; clk      ;
; N/A           ; None        ; -4.541 ns ; show ; temp_l[1]         ; clk      ;
; N/A           ; None        ; -4.546 ns ; show ; reset             ; clk      ;
; N/A           ; None        ; -4.550 ns ; show ; temp_l[0]         ; clk      ;
; N/A           ; None        ; -4.555 ns ; show ; temp_color.red    ; clk      ;
; N/A           ; None        ; -4.556 ns ; show ; temp_l[2]         ; clk      ;
; N/A           ; None        ; -4.732 ns ; show ; tempr             ; clk      ;
; N/A           ; None        ; -4.733 ns ; show ; tempt             ; clk      ;
; N/A           ; None        ; -4.822 ns ; show ; tempg             ; clk      ;
; N/A           ; None        ; -6.062 ns ; show ; temp_h[2]         ; clk      ;
; N/A           ; None        ; -6.062 ns ; show ; temp_h[3]         ; clk      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 11 23:44:35 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ControlB -c ControlB
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 175.5 MHz between source register "temp_h[2]" and destination register "temp_h[2]" (period= 5.698 ns)
    Info: + Longest register to register delay is 5.019 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h[2]'
        Info: 2: + IC(0.391 ns) + CELL(1.409 ns) = 2.059 ns; Loc. = LC2_14_I3; Fanout = 3; COMB Node = 'temp_l[0]~907'
        Info: 3: + IC(0.381 ns) + CELL(0.574 ns) = 3.014 ns; Loc. = LC7_14_I3; Fanout = 1; COMB Node = 'temp_l[0]~908'
        Info: 4: + IC(0.343 ns) + CELL(0.574 ns) = 3.931 ns; Loc. = LC8_14_I3; Fanout = 2; COMB Node = 'temp_l[0]~909'
        Info: 5: + IC(0.273 ns) + CELL(0.815 ns) = 5.019 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h[2]'
        Info: Total cell delay = 3.631 ns ( 72.35 % )
        Info: Total interconnect delay = 1.388 ns ( 27.65 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.697 ns
            Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h[2]'
            Info: Total cell delay = 1.676 ns ( 45.33 % )
            Info: Total interconnect delay = 2.021 ns ( 54.67 % )
        Info: - Longest clock path from clock "clk" to source register is 3.697 ns
            Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h[2]'
            Info: Total cell delay = 1.676 ns ( 45.33 % )
            Info: Total interconnect delay = 2.021 ns ( 54.67 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Micro setup delay of destination is 0.167 ns
Info: tsu for register "temp_h[2]" (data pin = "show", clock pin = "clk") is 6.605 ns
    Info: + Longest pin to register delay is 10.135 ns
        Info: 1: + IC(0.000 ns) + CELL(2.148 ns) = 2.148 ns; Loc. = PIN_224; Fanout = 16; PIN Node = 'show'
        Info: 2: + IC(5.471 ns) + CELL(1.428 ns) = 9.047 ns; Loc. = LC8_14_I3; Fanout = 2; COMB Node = 'temp_l[0]~909'
        Info: 3: + IC(0.273 ns) + CELL(0.815 ns) = 10.135 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h[2]'
        Info: Total cell delay = 4.391 ns ( 43.33 % )
        Info: Total interconnect delay = 5.744 ns ( 56.67 % )
    Info: + Micro setup delay of destination is 0.167 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.697 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h[2]'
        Info: Total cell delay = 1.676 ns ( 45.33 % )
        Info: Total interconnect delay = 2.021 ns ( 54.67 % )
Info: tco from clock "clk" to destination pin "timel[2]" through register "temp_l[2]" is 11.231 ns
    Info: + Longest clock path from clock "clk" to source register is 3.697 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC9_15_I3; Fanout = 6; REG Node = 'temp_l[2]'
        Info: Total cell delay = 1.676 ns ( 45.33 % )
        Info: Total interconnect delay = 2.021 ns ( 54.67 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Longest register to pin delay is 7.022 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC9_15_I3; Fanout = 6; REG Node = 'temp_l[2]'
        Info: 2: + IC(4.052 ns) + CELL(2.711 ns) = 7.022 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'timel[2]'
        Info: Total cell delay = 2.970 ns ( 42.30 % )
        Info: Total interconnect delay = 4.052 ns ( 57.70 % )
Info: th for register "temp_h[0]" (data pin = "show", clock pin = "clk") is -4.433 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.697 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC3_14_I3; Fanout = 6; REG Node = 'temp_h[0]'
        Info: Total cell delay = 1.676 ns ( 45.33 % )
        Info: Total interconnect delay = 2.021 ns ( 54.67 % )
    Info: + Micro hold delay of destination is 0.376 ns
    Info: - Shortest pin to register delay is 8.506 ns
        Info: 1: + IC(0.000 ns) + CELL(2.148 ns) = 2.148 ns; Loc. = PIN_224; Fanout = 16; PIN Node = 'show'
        Info: 2: + IC(5.543 ns) + CELL(0.815 ns) = 8.506 ns; Loc. = LC3_14_I3; Fanout = 6; REG Node = 'temp_h[0]'
        Info: Total cell delay = 2.963 ns ( 34.83 % )
        Info: Total interconnect delay = 5.543 ns ( 65.17 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Mon May 11 23:44:37 2009
    Info: Elapsed time: 00:00:02