controlb.tan.qmsg

vhdl语言编写的交通灯程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk timel\[2\] temp_l\[2\] 11.231 ns register " "Info: tco from clock \"clk\" to destination pin \"timel\[2\]\" through register \"temp_l\[2\]\" is 11.231 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.697 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 17 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.021 ns) + CELL(0.000 ns) 3.697 ns temp_l\[2\] 2 REG LC9_15_I3 6 " "Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC9_15_I3; Fanout = 6; REG Node = 'temp_l\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.021 ns" { clk temp_l[2] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.33 % ) " "Info: Total cell delay = 1.676 ns ( 45.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.021 ns ( 54.67 % ) " "Info: Total interconnect delay = 2.021 ns ( 54.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_l[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_l[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.022 ns + Longest register pin " "Info: + Longest register to pin delay is 7.022 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns temp_l\[2\] 1 REG LC9_15_I3 6 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC9_15_I3; Fanout = 6; REG Node = 'temp_l\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp_l[2] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.052 ns) + CELL(2.711 ns) 7.022 ns timel\[2\] 2 PIN PIN_17 0 " "Info: 2: + IC(4.052 ns) + CELL(2.711 ns) = 7.022 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'timel\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.763 ns" { temp_l[2] timel[2] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.970 ns ( 42.30 % ) " "Info: Total cell delay = 2.970 ns ( 42.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.052 ns ( 57.70 % ) " "Info: Total interconnect delay = 4.052 ns ( 57.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.022 ns" { temp_l[2] timel[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.022 ns" { temp_l[2] {} timel[2] {} } { 0.000ns 4.052ns } { 0.259ns 2.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_l[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_l[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.022 ns" { temp_l[2] timel[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.022 ns" { temp_l[2] {} timel[2] {} } { 0.000ns 4.052ns } { 0.259ns 2.711ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "temp_h\[0\] show clk -4.433 ns register " "Info: th for register \"temp_h\[0\]\" (data pin = \"show\", clock pin = \"clk\") is -4.433 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.697 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 17 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.021 ns) + CELL(0.000 ns) 3.697 ns temp_h\[0\] 2 REG LC3_14_I3 6 " "Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC3_14_I3; Fanout = 6; REG Node = 'temp_h\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.021 ns" { clk temp_h[0] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.33 % ) " "Info: Total cell delay = 1.676 ns ( 45.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.021 ns ( 54.67 % ) " "Info: Total interconnect delay = 2.021 ns ( 54.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[0] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.376 ns + " "Info: + Micro hold delay of destination is 0.376 ns" {  } { { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.506 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.506 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.148 ns) 2.148 ns show 1 PIN PIN_224 16 " "Info: 1: + IC(0.000 ns) + CELL(2.148 ns) = 2.148 ns; Loc. = PIN_224; Fanout = 16; PIN Node = 'show'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { show } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.543 ns) + CELL(0.815 ns) 8.506 ns temp_h\[0\] 2 REG LC3_14_I3 6 " "Info: 2: + IC(5.543 ns) + CELL(0.815 ns) = 8.506 ns; Loc. = LC3_14_I3; Fanout = 6; REG Node = 'temp_h\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.358 ns" { show temp_h[0] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.963 ns ( 34.83 % ) " "Info: Total cell delay = 2.963 ns ( 34.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.543 ns ( 65.17 % ) " "Info: Total interconnect delay = 5.543 ns ( 65.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.506 ns" { show temp_h[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.506 ns" { show {} show~out0 {} temp_h[0] {} } { 0.000ns 0.000ns 5.543ns } { 0.000ns 2.148ns 0.815ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[0] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.506 ns" { show temp_h[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.506 ns" { show {} show~out0 {} temp_h[0] {} } { 0.000ns 0.000ns 5.543ns } { 0.000ns 2.148ns 0.815ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 23:44:37 2009 " "Info: Processing ended: Mon May 11 23:44:37 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}