controlb.tan.qmsg

vhdl语言编写的交通灯程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register temp_h\[2\] register temp_h\[2\] 175.5 MHz 5.698 ns Internal " "Info: Clock \"clk\" has Internal fmax of 175.5 MHz between source register \"temp_h\[2\]\" and destination register \"temp_h\[2\]\" (period= 5.698 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.019 ns + Longest register register " "Info: + Longest register to register delay is 5.019 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns temp_h\[2\] 1 REG LC1_14_I3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp_h[2] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(1.409 ns) 2.059 ns temp_l\[0\]~907 2 COMB LC2_14_I3 3 " "Info: 2: + IC(0.391 ns) + CELL(1.409 ns) = 2.059 ns; Loc. = LC2_14_I3; Fanout = 3; COMB Node = 'temp_l\[0\]~907'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { temp_h[2] temp_l[0]~907 } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.574 ns) 3.014 ns temp_l\[0\]~908 3 COMB LC7_14_I3 1 " "Info: 3: + IC(0.381 ns) + CELL(0.574 ns) = 3.014 ns; Loc. = LC7_14_I3; Fanout = 1; COMB Node = 'temp_l\[0\]~908'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.955 ns" { temp_l[0]~907 temp_l[0]~908 } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.574 ns) 3.931 ns temp_l\[0\]~909 4 COMB LC8_14_I3 2 " "Info: 4: + IC(0.343 ns) + CELL(0.574 ns) = 3.931 ns; Loc. = LC8_14_I3; Fanout = 2; COMB Node = 'temp_l\[0\]~909'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.917 ns" { temp_l[0]~908 temp_l[0]~909 } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.273 ns) + CELL(0.815 ns) 5.019 ns temp_h\[2\] 5 REG LC1_14_I3 4 " "Info: 5: + IC(0.273 ns) + CELL(0.815 ns) = 5.019 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.088 ns" { temp_l[0]~909 temp_h[2] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.631 ns ( 72.35 % ) " "Info: Total cell delay = 3.631 ns ( 72.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.388 ns ( 27.65 % ) " "Info: Total interconnect delay = 1.388 ns ( 27.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.019 ns" { temp_h[2] temp_l[0]~907 temp_l[0]~908 temp_l[0]~909 temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.019 ns" { temp_h[2] {} temp_l[0]~907 {} temp_l[0]~908 {} temp_l[0]~909 {} temp_h[2] {} } { 0.000ns 0.391ns 0.381ns 0.343ns 0.273ns } { 0.259ns 1.409ns 0.574ns 0.574ns 0.815ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.697 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 17 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.021 ns) + CELL(0.000 ns) 3.697 ns temp_h\[2\] 2 REG LC1_14_I3 4 " "Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.021 ns" { clk temp_h[2] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.33 % ) " "Info: Total cell delay = 1.676 ns ( 45.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.021 ns ( 54.67 % ) " "Info: Total interconnect delay = 2.021 ns ( 54.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.697 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 17 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.021 ns) + CELL(0.000 ns) 3.697 ns temp_h\[2\] 2 REG LC1_14_I3 4 " "Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.021 ns" { clk temp_h[2] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.33 % ) " "Info: Total cell delay = 1.676 ns ( 45.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.021 ns ( 54.67 % ) " "Info: Total interconnect delay = 2.021 ns ( 54.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.167 ns + " "Info: + Micro setup delay of destination is 0.167 ns" {  } { { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.019 ns" { temp_h[2] temp_l[0]~907 temp_l[0]~908 temp_l[0]~909 temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.019 ns" { temp_h[2] {} temp_l[0]~907 {} temp_l[0]~908 {} temp_l[0]~909 {} temp_h[2] {} } { 0.000ns 0.391ns 0.381ns 0.343ns 0.273ns } { 0.259ns 1.409ns 0.574ns 0.574ns 0.815ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "temp_h\[2\] show clk 6.605 ns register " "Info: tsu for register \"temp_h\[2\]\" (data pin = \"show\", clock pin = \"clk\") is 6.605 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.135 ns + Longest pin register " "Info: + Longest pin to register delay is 10.135 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.148 ns) 2.148 ns show 1 PIN PIN_224 16 " "Info: 1: + IC(0.000 ns) + CELL(2.148 ns) = 2.148 ns; Loc. = PIN_224; Fanout = 16; PIN Node = 'show'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { show } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.471 ns) + CELL(1.428 ns) 9.047 ns temp_l\[0\]~909 2 COMB LC8_14_I3 2 " "Info: 2: + IC(5.471 ns) + CELL(1.428 ns) = 9.047 ns; Loc. = LC8_14_I3; Fanout = 2; COMB Node = 'temp_l\[0\]~909'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.899 ns" { show temp_l[0]~909 } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.273 ns) + CELL(0.815 ns) 10.135 ns temp_h\[2\] 3 REG LC1_14_I3 4 " "Info: 3: + IC(0.273 ns) + CELL(0.815 ns) = 10.135 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.088 ns" { temp_l[0]~909 temp_h[2] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.391 ns ( 43.33 % ) " "Info: Total cell delay = 4.391 ns ( 43.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.744 ns ( 56.67 % ) " "Info: Total interconnect delay = 5.744 ns ( 56.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.135 ns" { show temp_l[0]~909 temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.135 ns" { show {} show~out0 {} temp_l[0]~909 {} temp_h[2] {} } { 0.000ns 0.000ns 5.471ns 0.273ns } { 0.000ns 2.148ns 1.428ns 0.815ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.167 ns + " "Info: + Micro setup delay of destination is 0.167 ns" {  } { { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.697 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 17 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.021 ns) + CELL(0.000 ns) 3.697 ns temp_h\[2\] 2 REG LC1_14_I3 4 " "Info: 2: + IC(2.021 ns) + CELL(0.000 ns) = 3.697 ns; Loc. = LC1_14_I3; Fanout = 4; REG Node = 'temp_h\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.021 ns" { clk temp_h[2] } "NODE_NAME" } } { "ControlB.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m5/ControlB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.33 % ) " "Info: Total cell delay = 1.676 ns ( 45.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.021 ns ( 54.67 % ) " "Info: Total interconnect delay = 2.021 ns ( 54.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.135 ns" { show temp_l[0]~909 temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.135 ns" { show {} show~out0 {} temp_l[0]~909 {} temp_h[2] {} } { 0.000ns 0.000ns 5.471ns 0.273ns } { 0.000ns 2.148ns 1.428ns 0.815ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.697 ns" { clk temp_h[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.697 ns" { clk {} clk~out0 {} temp_h[2] {} } { 0.000ns 0.000ns 2.021ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}