controla.tan.rpt

vhdl语言编写的交通灯程序

; Slack ; Required tco ; Actual tco ; From      ; To       ; From Clock ;
+-------+--------------+------------+-----------+----------+------------+
; N/A   ; None         ; 12.950 ns  ; temp_h[0] ; timeh[0] ; clk        ;
; N/A   ; None         ; 12.836 ns  ; temp_l[0] ; timel[0] ; clk        ;
; N/A   ; None         ; 9.619 ns   ; temp_l[1] ; timel[1] ; clk        ;
; N/A   ; None         ; 9.599 ns   ; temp_l[2] ; timel[2] ; clk        ;
; N/A   ; None         ; 9.570 ns   ; tempy     ; y        ; clk        ;
; N/A   ; None         ; 9.569 ns   ; temp_h[3] ; timeh[3] ; clk        ;
; N/A   ; None         ; 9.554 ns   ; temp_l[3] ; timel[3] ; clk        ;
; N/A   ; None         ; 9.527 ns   ; tempg     ; g        ; clk        ;
; N/A   ; None         ; 9.517 ns   ; temp_h[2] ; timeh[2] ; clk        ;
; N/A   ; None         ; 9.516 ns   ; temp_h[1] ; timeh[1] ; clk        ;
; N/A   ; None         ; 8.570 ns   ; tempt     ; t        ; clk        ;
; N/A   ; None         ; 8.567 ns   ; tempr     ; r        ; clk        ;
+-------+--------------+------------+-----------+----------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; -4.491 ns ; show ; temp_h[0]         ; clk      ;
; N/A           ; None        ; -4.500 ns ; show ; temp_h[1]         ; clk      ;
; N/A           ; None        ; -4.519 ns ; show ; temp_color.turn   ; clk      ;
; N/A           ; None        ; -4.521 ns ; show ; temp_color.red    ; clk      ;
; N/A           ; None        ; -4.524 ns ; show ; temp_color.green  ; clk      ;
; N/A           ; None        ; -4.525 ns ; show ; reset             ; clk      ;
; N/A           ; None        ; -4.525 ns ; show ; temp_color.yellow ; clk      ;
; N/A           ; None        ; -4.585 ns ; show ; temp_l[0]         ; clk      ;
; N/A           ; None        ; -4.594 ns ; show ; temp_l[3]         ; clk      ;
; N/A           ; None        ; -4.607 ns ; show ; temp_l[1]         ; clk      ;
; N/A           ; None        ; -4.612 ns ; show ; temp_l[2]         ; clk      ;
; N/A           ; None        ; -4.762 ns ; show ; tempt             ; clk      ;
; N/A           ; None        ; -4.784 ns ; show ; tempg             ; clk      ;
; N/A           ; None        ; -4.795 ns ; show ; tempy             ; clk      ;
; N/A           ; None        ; -4.796 ns ; show ; tempr             ; clk      ;
; N/A           ; None        ; -6.104 ns ; show ; temp_h[2]         ; clk      ;
; N/A           ; None        ; -6.104 ns ; show ; temp_h[3]         ; clk      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 11 23:37:01 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ControlA -c ControlA
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 159.8 MHz between source register "temp_l[2]" and destination register "temp_h[2]" (period= 6.258 ns)
    Info: + Longest register to register delay is 5.579 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC5_13_C4; Fanout = 6; REG Node = 'temp_l[2]'
        Info: 2: + IC(1.244 ns) + CELL(1.278 ns) = 2.781 ns; Loc. = LC6_13_C4; Fanout = 3; COMB Node = 'Mux11~33'
        Info: 3: + IC(0.287 ns) + CELL(1.409 ns) = 4.477 ns; Loc. = LC4_12_C4; Fanout = 2; COMB Node = 'temp_l[0]~909'
        Info: 4: + IC(0.287 ns) + CELL(0.815 ns) = 5.579 ns; Loc. = LC3_12_C4; Fanout = 4; REG Node = 'temp_h[2]'
        Info: Total cell delay = 3.761 ns ( 67.41 % )
        Info: Total interconnect delay = 1.818 ns ( 32.59 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.709 ns
            Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC3_12_C4; Fanout = 4; REG Node = 'temp_h[2]'
            Info: Total cell delay = 1.676 ns ( 45.19 % )
            Info: Total interconnect delay = 2.033 ns ( 54.81 % )
        Info: - Longest clock path from clock "clk" to source register is 3.709 ns
            Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC5_13_C4; Fanout = 6; REG Node = 'temp_l[2]'
            Info: Total cell delay = 1.676 ns ( 45.19 % )
            Info: Total interconnect delay = 2.033 ns ( 54.81 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Micro setup delay of destination is 0.167 ns
Info: tsu for register "temp_h[2]" (data pin = "show", clock pin = "clk") is 6.647 ns
    Info: + Longest pin to register delay is 10.189 ns
        Info: 1: + IC(0.000 ns) + CELL(2.148 ns) = 2.148 ns; Loc. = PIN_235; Fanout = 16; PIN Node = 'show'
        Info: 2: + IC(5.511 ns) + CELL(1.428 ns) = 9.087 ns; Loc. = LC4_12_C4; Fanout = 2; COMB Node = 'temp_l[0]~909'
        Info: 3: + IC(0.287 ns) + CELL(0.815 ns) = 10.189 ns; Loc. = LC3_12_C4; Fanout = 4; REG Node = 'temp_h[2]'
        Info: Total cell delay = 4.391 ns ( 43.10 % )
        Info: Total interconnect delay = 5.798 ns ( 56.90 % )
    Info: + Micro setup delay of destination is 0.167 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.709 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC3_12_C4; Fanout = 4; REG Node = 'temp_h[2]'
        Info: Total cell delay = 1.676 ns ( 45.19 % )
        Info: Total interconnect delay = 2.033 ns ( 54.81 % )
Info: tco from clock "clk" to destination pin "timeh[0]" through register "temp_h[0]" is 12.950 ns
    Info: + Longest clock path from clock "clk" to source register is 3.709 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC1_12_C4; Fanout = 6; REG Node = 'temp_h[0]'
        Info: Total cell delay = 1.676 ns ( 45.19 % )
        Info: Total interconnect delay = 2.033 ns ( 54.81 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Longest register to pin delay is 8.729 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC1_12_C4; Fanout = 6; REG Node = 'temp_h[0]'
        Info: 2: + IC(5.759 ns) + CELL(2.711 ns) = 8.729 ns; Loc. = PIN_171; Fanout = 0; PIN Node = 'timeh[0]'
        Info: Total cell delay = 2.970 ns ( 34.02 % )
        Info: Total interconnect delay = 5.759 ns ( 65.98 % )
Info: th for register "temp_h[0]" (data pin = "show", clock pin = "clk") is -4.491 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.709 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC1_12_C4; Fanout = 6; REG Node = 'temp_h[0]'
        Info: Total cell delay = 1.676 ns ( 45.19 % )
        Info: Total interconnect delay = 2.033 ns ( 54.81 % )
    Info: + Micro hold delay of destination is 0.376 ns
    Info: - Shortest pin to register delay is 8.576 ns
        Info: 1: + IC(0.000 ns) + CELL(2.148 ns) = 2.148 ns; Loc. = PIN_235; Fanout = 16; PIN Node = 'show'
        Info: 2: + IC(5.613 ns) + CELL(0.815 ns) = 8.576 ns; Loc. = LC1_12_C4; Fanout = 6; REG Node = 'temp_h[0]'
        Info: Total cell delay = 2.963 ns ( 34.55 % )
        Info: Total interconnect delay = 5.613 ns ( 65.45 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Mon May 11 23:37:03 2009
    Info: Elapsed time: 00:00:02