debounce.tan.qmsg

vhdl语言编写的交通灯程序

{ "Info" "ITDB_TH_RESULT" "temp1 key clk -3.013 ns register " "Info: th for register \"temp1\" (data pin = \"key\", clock pin = \"clk\") is -3.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.713 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 3 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.037 ns) + CELL(0.000 ns) 3.713 ns temp1 2 REG LC3_15_A4 2 " "Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.037 ns" { clk temp1 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.14 % ) " "Info: Total cell delay = 1.676 ns ( 45.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.037 ns ( 54.86 % ) " "Info: Total interconnect delay = 2.037 ns ( 54.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp1 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.376 ns + " "Info: + Micro hold delay of destination is 0.376 ns" {  } { { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.102 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.070 ns) 2.070 ns key 1 PIN PIN_3 1 " "Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'key'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.764 ns) + CELL(0.268 ns) 7.102 ns temp1 2 REG LC3_15_A4 2 " "Info: 2: + IC(4.764 ns) + CELL(0.268 ns) = 7.102 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.032 ns" { key temp1 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.338 ns ( 32.92 % ) " "Info: Total cell delay = 2.338 ns ( 32.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.764 ns ( 67.08 % ) " "Info: Total interconnect delay = 4.764 ns ( 67.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.102 ns" { key temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.102 ns" { key {} key~out0 {} temp1 {} } { 0.000ns 0.000ns 4.764ns } { 0.000ns 2.070ns 0.268ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp1 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.102 ns" { key temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.102 ns" { key {} key~out0 {} temp1 {} } { 0.000ns 0.000ns 4.764ns } { 0.000ns 2.070ns 0.268ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 23:25:08 2009 " "Info: Processing ended: Mon May 11 23:25:08 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}