debounce.tan.qmsg

vhdl语言编写的交通灯程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 6 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register temp1 temp2 233.7 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 233.7 MHz between source register \"temp1\" and destination register \"temp2\"" { { "Info" "ITDB_CLOCK_RATE" "clock 4.279 ns " "Info: fmax restricted to clock pin edge rate 4.279 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.803 ns + Longest register register " "Info: + Longest register to register delay is 0.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns temp1 1 REG LC3_15_A4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp1 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.276 ns) + CELL(0.268 ns) 0.803 ns temp2 2 REG LC6_15_A4 1 " "Info: 2: + IC(0.276 ns) + CELL(0.268 ns) = 0.803 ns; Loc. = LC6_15_A4; Fanout = 1; REG Node = 'temp2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.544 ns" { temp1 temp2 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.527 ns ( 65.63 % ) " "Info: Total cell delay = 0.527 ns ( 65.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.276 ns ( 34.37 % ) " "Info: Total interconnect delay = 0.276 ns ( 34.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { temp1 temp2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.803 ns" { temp1 {} temp2 {} } { 0.000ns 0.276ns } { 0.259ns 0.268ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.713 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 3 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.037 ns) + CELL(0.000 ns) 3.713 ns temp2 2 REG LC6_15_A4 1 " "Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC6_15_A4; Fanout = 1; REG Node = 'temp2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.037 ns" { clk temp2 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.14 % ) " "Info: Total cell delay = 1.676 ns ( 45.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.037 ns ( 54.86 % ) " "Info: Total interconnect delay = 2.037 ns ( 54.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp2 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.713 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 3 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.037 ns) + CELL(0.000 ns) 3.713 ns temp1 2 REG LC3_15_A4 2 " "Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.037 ns" { clk temp1 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.14 % ) " "Info: Total cell delay = 1.676 ns ( 45.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.037 ns ( 54.86 % ) " "Info: Total interconnect delay = 2.037 ns ( 54.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp1 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp2 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp1 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.167 ns + " "Info: + Micro setup delay of destination is 0.167 ns" {  } { { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { temp1 temp2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.803 ns" { temp1 {} temp2 {} } { 0.000ns 0.276ns } { 0.259ns 0.268ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp2 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp1 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { temp2 {} } { 0.000ns } { 0.259ns } "" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "temp1 key clk 3.556 ns register " "Info: tsu for register \"temp1\" (data pin = \"key\", clock pin = \"clk\") is 3.556 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.102 ns + Longest pin register " "Info: + Longest pin to register delay is 7.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.070 ns) 2.070 ns key 1 PIN PIN_3 1 " "Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'key'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.764 ns) + CELL(0.268 ns) 7.102 ns temp1 2 REG LC3_15_A4 2 " "Info: 2: + IC(4.764 ns) + CELL(0.268 ns) = 7.102 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.032 ns" { key temp1 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.338 ns ( 32.92 % ) " "Info: Total cell delay = 2.338 ns ( 32.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.764 ns ( 67.08 % ) " "Info: Total interconnect delay = 4.764 ns ( 67.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.102 ns" { key temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.102 ns" { key {} key~out0 {} temp1 {} } { 0.000ns 0.000ns 4.764ns } { 0.000ns 2.070ns 0.268ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.167 ns + " "Info: + Micro setup delay of destination is 0.167 ns" {  } { { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.713 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 3 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.037 ns) + CELL(0.000 ns) 3.713 ns temp1 2 REG LC3_15_A4 2 " "Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.037 ns" { clk temp1 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.14 % ) " "Info: Total cell delay = 1.676 ns ( 45.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.037 ns ( 54.86 % ) " "Info: Total interconnect delay = 2.037 ns ( 54.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp1 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.102 ns" { key temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.102 ns" { key {} key~out0 {} temp1 {} } { 0.000ns 0.000ns 4.764ns } { 0.000ns 2.070ns 0.268ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp1 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk key_out temp2 9.212 ns register " "Info: tco from clock \"clk\" to destination pin \"key_out\" through register \"temp2\" is 9.212 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.713 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 3 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.037 ns) + CELL(0.000 ns) 3.713 ns temp2 2 REG LC6_15_A4 1 " "Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC6_15_A4; Fanout = 1; REG Node = 'temp2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.037 ns" { clk temp2 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.14 % ) " "Info: Total cell delay = 1.676 ns ( 45.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.037 ns ( 54.86 % ) " "Info: Total interconnect delay = 2.037 ns ( 54.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp2 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.987 ns + Longest register pin " "Info: + Longest register to pin delay is 4.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns temp2 1 REG LC6_15_A4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC6_15_A4; Fanout = 1; REG Node = 'temp2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp2 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(1.409 ns) 1.927 ns key_out~22 2 COMB LC5_15_A4 1 " "Info: 2: + IC(0.259 ns) + CELL(1.409 ns) = 1.927 ns; Loc. = LC5_15_A4; Fanout = 1; COMB Node = 'key_out~22'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.668 ns" { temp2 key_out~22 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(2.801 ns) 4.987 ns key_out 3 PIN PIN_230 0 " "Info: 3: + IC(0.259 ns) + CELL(2.801 ns) = 4.987 ns; Loc. = PIN_230; Fanout = 0; PIN Node = 'key_out'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { key_out~22 key_out } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.469 ns ( 89.61 % ) " "Info: Total cell delay = 4.469 ns ( 89.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.518 ns ( 10.39 % ) " "Info: Total interconnect delay = 0.518 ns ( 10.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.987 ns" { temp2 key_out~22 key_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.987 ns" { temp2 {} key_out~22 {} key_out {} } { 0.000ns 0.259ns 0.259ns } { 0.259ns 1.409ns 2.801ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { clk temp2 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { clk {} clk~out0 {} temp2 {} } { 0.000ns 0.000ns 2.037ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.987 ns" { temp2 key_out~22 key_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.987 ns" { temp2 {} key_out~22 {} key_out {} } { 0.000ns 0.259ns 0.259ns } { 0.259ns 1.409ns 2.801ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk key_out 7.667 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"key_out\" is 7.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 3 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.653 ns) + CELL(1.278 ns) 4.607 ns key_out~22 2 COMB LC5_15_A4 1 " "Info: 2: + IC(1.653 ns) + CELL(1.278 ns) = 4.607 ns; Loc. = LC5_15_A4; Fanout = 1; COMB Node = 'key_out~22'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.931 ns" { clk key_out~22 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(2.801 ns) 7.667 ns key_out 3 PIN PIN_230 0 " "Info: 3: + IC(0.259 ns) + CELL(2.801 ns) = 7.667 ns; Loc. = PIN_230; Fanout = 0; PIN Node = 'key_out'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.060 ns" { key_out~22 key_out } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Debounce.vhd" "" { Text "D:/altera/72/quartus/bin/Debounce.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.755 ns ( 75.06 % ) " "Info: Total cell delay = 5.755 ns ( 75.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.912 ns ( 24.94 % ) " "Info: Total interconnect delay = 1.912 ns ( 24.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.667 ns" { clk key_out~22 key_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.667 ns" { clk {} clk~out0 {} key_out~22 {} key_out {} } { 0.000ns 0.000ns 1.653ns 0.259ns } { 0.000ns 1.676ns 1.278ns 2.801ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}