debounce.tan.rpt

vhdl语言编写的交通灯程序

; tco                                                              ;
+-------+--------------+------------+-------+---------+------------+
; Slack ; Required tco ; Actual tco ; From  ; To      ; From Clock ;
+-------+--------------+------------+-------+---------+------------+
; N/A   ; None         ; 9.212 ns   ; temp2 ; key_out ; clk        ;
; N/A   ; None         ; 8.394 ns   ; temp1 ; key_out ; clk        ;
+-------+--------------+------------+-------+---------+------------+


+--------------------------------------------------------------+
; tpd                                                          ;
+-------+-------------------+-----------------+------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To      ;
+-------+-------------------+-----------------+------+---------+
; N/A   ; None              ; 7.667 ns        ; clk  ; key_out ;
+-------+-------------------+-----------------+------+---------+


+-------------------------------------------------------------------+
; th                                                                ;
+---------------+-------------+-----------+------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To    ; To Clock ;
+---------------+-------------+-----------+------+-------+----------+
; N/A           ; None        ; -3.013 ns ; key  ; temp1 ; clk      ;
+---------------+-------------+-----------+------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 11 23:25:06 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Debounce -c Debounce
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 233.7 MHz between source register "temp1" and destination register "temp2"
    Info: fmax restricted to clock pin edge rate 4.279 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.803 ns
            Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'
            Info: 2: + IC(0.276 ns) + CELL(0.268 ns) = 0.803 ns; Loc. = LC6_15_A4; Fanout = 1; REG Node = 'temp2'
            Info: Total cell delay = 0.527 ns ( 65.63 % )
            Info: Total interconnect delay = 0.276 ns ( 34.37 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.713 ns
                Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC6_15_A4; Fanout = 1; REG Node = 'temp2'
                Info: Total cell delay = 1.676 ns ( 45.14 % )
                Info: Total interconnect delay = 2.037 ns ( 54.86 % )
            Info: - Longest clock path from clock "clk" to source register is 3.713 ns
                Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'
                Info: Total cell delay = 1.676 ns ( 45.14 % )
                Info: Total interconnect delay = 2.037 ns ( 54.86 % )
        Info: + Micro clock to output delay of source is 0.512 ns
        Info: + Micro setup delay of destination is 0.167 ns
Info: tsu for register "temp1" (data pin = "key", clock pin = "clk") is 3.556 ns
    Info: + Longest pin to register delay is 7.102 ns
        Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'key'
        Info: 2: + IC(4.764 ns) + CELL(0.268 ns) = 7.102 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'
        Info: Total cell delay = 2.338 ns ( 32.92 % )
        Info: Total interconnect delay = 4.764 ns ( 67.08 % )
    Info: + Micro setup delay of destination is 0.167 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.713 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'
        Info: Total cell delay = 1.676 ns ( 45.14 % )
        Info: Total interconnect delay = 2.037 ns ( 54.86 % )
Info: tco from clock "clk" to destination pin "key_out" through register "temp2" is 9.212 ns
    Info: + Longest clock path from clock "clk" to source register is 3.713 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC6_15_A4; Fanout = 1; REG Node = 'temp2'
        Info: Total cell delay = 1.676 ns ( 45.14 % )
        Info: Total interconnect delay = 2.037 ns ( 54.86 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Longest register to pin delay is 4.987 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC6_15_A4; Fanout = 1; REG Node = 'temp2'
        Info: 2: + IC(0.259 ns) + CELL(1.409 ns) = 1.927 ns; Loc. = LC5_15_A4; Fanout = 1; COMB Node = 'key_out~22'
        Info: 3: + IC(0.259 ns) + CELL(2.801 ns) = 4.987 ns; Loc. = PIN_230; Fanout = 0; PIN Node = 'key_out'
        Info: Total cell delay = 4.469 ns ( 89.61 % )
        Info: Total interconnect delay = 0.518 ns ( 10.39 % )
Info: Longest tpd from source pin "clk" to destination pin "key_out" is 7.667 ns
    Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'
    Info: 2: + IC(1.653 ns) + CELL(1.278 ns) = 4.607 ns; Loc. = LC5_15_A4; Fanout = 1; COMB Node = 'key_out~22'
    Info: 3: + IC(0.259 ns) + CELL(2.801 ns) = 7.667 ns; Loc. = PIN_230; Fanout = 0; PIN Node = 'key_out'
    Info: Total cell delay = 5.755 ns ( 75.06 % )
    Info: Total interconnect delay = 1.912 ns ( 24.94 % )
Info: th for register "temp1" (data pin = "key", clock pin = "clk") is -3.013 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.713 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(2.037 ns) + CELL(0.000 ns) = 3.713 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'
        Info: Total cell delay = 1.676 ns ( 45.14 % )
        Info: Total interconnect delay = 2.037 ns ( 54.86 % )
    Info: + Micro hold delay of destination is 0.376 ns
    Info: - Shortest pin to register delay is 7.102 ns
        Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'key'
        Info: 2: + IC(4.764 ns) + CELL(0.268 ns) = 7.102 ns; Loc. = LC3_15_A4; Fanout = 2; REG Node = 'temp1'
        Info: Total cell delay = 2.338 ns ( 32.92 % )
        Info: Total interconnect delay = 4.764 ns ( 67.08 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Mon May 11 23:25:08 2009
    Info: Elapsed time: 00:00:02