prev_cmp_frequency1.tan.qmsg

vhdl语言编写的交通灯程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register temp\[3\] register temp\[19\] 119.09 MHz 8.397 ns Internal " "Info: Clock \"clk\" has Internal fmax of 119.09 MHz between source register \"temp\[3\]\" and destination register \"temp\[19\]\" (period= 8.397 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.718 ns + Longest register register " "Info: + Longest register to register delay is 7.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns temp\[3\] 1 REG LC2_3_L4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC2_3_L4; Fanout = 3; REG Node = 'temp\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp[3] } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.280 ns) + CELL(1.798 ns) 2.337 ns Add0~307 2 COMB LC4_4_L4 2 " "Info: 2: + IC(0.280 ns) + CELL(1.798 ns) = 2.337 ns; Loc. = LC4_4_L4; Fanout = 2; COMB Node = 'Add0~307'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.078 ns" { temp[3] Add0~307 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.492 ns Add0~310 3 COMB LC5_4_L4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 2.492 ns; Loc. = LC5_4_L4; Fanout = 2; COMB Node = 'Add0~310'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~307 Add0~310 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.647 ns Add0~313 4 COMB LC6_4_L4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 2.647 ns; Loc. = LC6_4_L4; Fanout = 2; COMB Node = 'Add0~313'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~310 Add0~313 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.802 ns Add0~316 5 COMB LC7_4_L4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.155 ns) = 2.802 ns; Loc. = LC7_4_L4; Fanout = 2; COMB Node = 'Add0~316'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~313 Add0~316 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.957 ns Add0~298 6 COMB LC8_4_L4 2 " "Info: 6: + IC(0.000 ns) + CELL(0.155 ns) = 2.957 ns; Loc. = LC8_4_L4; Fanout = 2; COMB Node = 'Add0~298'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~316 Add0~298 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 3.112 ns Add0~301 7 COMB LC9_4_L4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.155 ns) = 3.112 ns; Loc. = LC9_4_L4; Fanout = 2; COMB Node = 'Add0~301'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~298 Add0~301 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 3.267 ns Add0~295 8 COMB LC10_4_L4 2 " "Info: 8: + IC(0.000 ns) + CELL(0.155 ns) = 3.267 ns; Loc. = LC10_4_L4; Fanout = 2; COMB Node = 'Add0~295'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~301 Add0~295 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.155 ns) 4.200 ns Add0~304 9 COMB LC1_6_L4 2 " "Info: 9: + IC(0.778 ns) + CELL(0.155 ns) = 4.200 ns; Loc. = LC1_6_L4; Fanout = 2; COMB Node = 'Add0~304'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.933 ns" { Add0~295 Add0~304 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.355 ns Add0~328 10 COMB LC2_6_L4 2 " "Info: 10: + IC(0.000 ns) + CELL(0.155 ns) = 4.355 ns; Loc. = LC2_6_L4; Fanout = 2; COMB Node = 'Add0~328'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~304 Add0~328 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.510 ns Add0~337 11 COMB LC3_6_L4 2 " "Info: 11: + IC(0.000 ns) + CELL(0.155 ns) = 4.510 ns; Loc. = LC3_6_L4; Fanout = 2; COMB Node = 'Add0~337'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~328 Add0~337 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.665 ns Add0~334 12 COMB LC4_6_L4 2 " "Info: 12: + IC(0.000 ns) + CELL(0.155 ns) = 4.665 ns; Loc. = LC4_6_L4; Fanout = 2; COMB Node = 'Add0~334'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~337 Add0~334 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.820 ns Add0~331 13 COMB LC5_6_L4 2 " "Info: 13: + IC(0.000 ns) + CELL(0.155 ns) = 4.820 ns; Loc. = LC5_6_L4; Fanout = 2; COMB Node = 'Add0~331'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~334 Add0~331 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.975 ns Add0~292 14 COMB LC6_6_L4 2 " "Info: 14: + IC(0.000 ns) + CELL(0.155 ns) = 4.975 ns; Loc. = LC6_6_L4; Fanout = 2; COMB Node = 'Add0~292'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~331 Add0~292 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.130 ns Add0~289 15 COMB LC7_6_L4 2 " "Info: 15: + IC(0.000 ns) + CELL(0.155 ns) = 5.130 ns; Loc. = LC7_6_L4; Fanout = 2; COMB Node = 'Add0~289'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~292 Add0~289 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.285 ns Add0~286 16 COMB LC8_6_L4 2 " "Info: 16: + IC(0.000 ns) + CELL(0.155 ns) = 5.285 ns; Loc. = LC8_6_L4; Fanout = 2; COMB Node = 'Add0~286'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~289 Add0~286 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.440 ns Add0~283 17 COMB LC9_6_L4 1 " "Info: 17: + IC(0.000 ns) + CELL(0.155 ns) = 5.440 ns; Loc. = LC9_6_L4; Fanout = 1; COMB Node = 'Add0~283'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~286 Add0~283 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 6.460 ns Add0~279 18 COMB LC10_6_L4 1 " "Info: 18: + IC(0.000 ns) + CELL(1.020 ns) = 6.460 ns; Loc. = LC10_6_L4; Fanout = 1; COMB Node = 'Add0~279'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.020 ns" { Add0~283 Add0~279 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.992 ns) 7.718 ns temp\[19\] 19 REG LC3_7_L4 2 " "Info: 19: + IC(0.266 ns) + CELL(0.992 ns) = 7.718 ns; Loc. = LC3_7_L4; Fanout = 2; REG Node = 'temp\[19\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.258 ns" { Add0~279 temp[19] } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.394 ns ( 82.85 % ) " "Info: Total cell delay = 6.394 ns ( 82.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.324 ns ( 17.15 % ) " "Info: Total interconnect delay = 1.324 ns ( 17.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.718 ns" { temp[3] Add0~307 Add0~310 Add0~313 Add0~316 Add0~298 Add0~301 Add0~295 Add0~304 Add0~328 Add0~337 Add0~334 Add0~331 Add0~292 Add0~289 Add0~286 Add0~283 Add0~279 temp[19] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.718 ns" { temp[3] {} Add0~307 {} Add0~310 {} Add0~313 {} Add0~316 {} Add0~298 {} Add0~301 {} Add0~295 {} Add0~304 {} Add0~328 {} Add0~337 {} Add0~334 {} Add0~331 {} Add0~292 {} Add0~289 {} Add0~286 {} Add0~283 {} Add0~279 {} temp[19] {} } { 0.000ns 0.280ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.778ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.266ns } { 0.259ns 1.798ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 1.020ns 0.992ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.699 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 21 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.023 ns) + CELL(0.000 ns) 3.699 ns temp\[19\] 2 REG LC3_7_L4 2 " "Info: 2: + IC(2.023 ns) + CELL(0.000 ns) = 3.699 ns; Loc. = LC3_7_L4; Fanout = 2; REG Node = 'temp\[19\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.023 ns" { clk temp[19] } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.31 % ) " "Info: Total cell delay = 1.676 ns ( 45.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.023 ns ( 54.69 % ) " "Info: Total interconnect delay = 2.023 ns ( 54.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { clk temp[19] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { clk {} clk~out0 {} temp[19] {} } { 0.000ns 0.000ns 2.023ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.699 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 21 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.023 ns) + CELL(0.000 ns) 3.699 ns temp\[3\] 2 REG LC2_3_L4 3 " "Info: 2: + IC(2.023 ns) + CELL(0.000 ns) = 3.699 ns; Loc. = LC2_3_L4; Fanout = 3; REG Node = 'temp\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.023 ns" { clk temp[3] } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.31 % ) " "Info: Total cell delay = 1.676 ns ( 45.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.023 ns ( 54.69 % ) " "Info: Total interconnect delay = 2.023 ns ( 54.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { clk temp[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { clk {} clk~out0 {} temp[3] {} } { 0.000ns 0.000ns 2.023ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { clk temp[19] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { clk {} clk~out0 {} temp[19] {} } { 0.000ns 0.000ns 2.023ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { clk temp[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { clk {} clk~out0 {} temp[3] {} } { 0.000ns 0.000ns 2.023ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.167 ns + " "Info: + Micro setup delay of destination is 0.167 ns" {  } { { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.718 ns" { temp[3] Add0~307 Add0~310 Add0~313 Add0~316 Add0~298 Add0~301 Add0~295 Add0~304 Add0~328 Add0~337 Add0~334 Add0~331 Add0~292 Add0~289 Add0~286 Add0~283 Add0~279 temp[19] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.718 ns" { temp[3] {} Add0~307 {} Add0~310 {} Add0~313 {} Add0~316 {} Add0~298 {} Add0~301 {} Add0~295 {} Add0~304 {} Add0~328 {} Add0~337 {} Add0~334 {} Add0~331 {} Add0~292 {} Add0~289 {} Add0~286 {} Add0~283 {} Add0~279 {} temp[19] {} } { 0.000ns 0.280ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.778ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.266ns } { 0.259ns 1.798ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 1.020ns 0.992ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { clk temp[19] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { clk {} clk~out0 {} temp[19] {} } { 0.000ns 0.000ns 2.023ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { clk temp[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { clk {} clk~out0 {} temp[3] {} } { 0.000ns 0.000ns 2.023ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_out clk_out~reg0 7.440 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_out\" through register \"clk_out~reg0\" is 7.440 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.699 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 21 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 21; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.023 ns) + CELL(0.000 ns) 3.699 ns clk_out~reg0 2 REG LC3_1_L4 1 " "Info: 2: + IC(2.023 ns) + CELL(0.000 ns) = 3.699 ns; Loc. = LC3_1_L4; Fanout = 1; REG Node = 'clk_out~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.023 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.31 % ) " "Info: Total cell delay = 1.676 ns ( 45.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.023 ns ( 54.69 % ) " "Info: Total interconnect delay = 2.023 ns ( 54.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { clk {} clk~out0 {} clk_out~reg0 {} } { 0.000ns 0.000ns 2.023ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.229 ns + Longest register pin " "Info: + Longest register to pin delay is 3.229 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns clk_out~reg0 1 REG LC3_1_L4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC3_1_L4; Fanout = 1; REG Node = 'clk_out~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(2.711 ns) 3.229 ns clk_out 2 PIN PIN_43 0 " "Info: 2: + IC(0.259 ns) + CELL(2.711 ns) = 3.229 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'clk_out'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.970 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.970 ns ( 91.98 % ) " "Info: Total cell delay = 2.970 ns ( 91.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.259 ns ( 8.02 % ) " "Info: Total interconnect delay = 0.259 ns ( 8.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.229 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.229 ns" { clk_out~reg0 {} clk_out {} } { 0.000ns 0.259ns } { 0.259ns 2.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.699 ns" { clk {} clk~out0 {} clk_out~reg0 {} } { 0.000ns 0.000ns 2.023ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.229 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.229 ns" { clk_out~reg0 {} clk_out {} } { 0.000ns 0.259ns } { 0.259ns 2.711ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 23:05:08 2009 " "Info: Processing ended: Mon May 11 23:05:08 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}