frequency1.tan.qmsg

vhdl语言编写的交通灯程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register temp\[1\] clk_out~reg0 233.7 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 233.7 MHz between source register \"temp\[1\]\" and destination register \"clk_out~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 4.279 ns " "Info: fmax restricted to clock pin edge rate 4.279 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.720 ns + Longest register register " "Info: + Longest register to register delay is 1.720 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns temp\[1\] 1 REG LC5_7_C1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC5_7_C1; Fanout = 4; REG Node = 'temp\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp[1] } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(1.140 ns) 1.720 ns clk_out~reg0 2 REG LC6_7_C1 1 " "Info: 2: + IC(0.321 ns) + CELL(1.140 ns) = 1.720 ns; Loc. = LC6_7_C1; Fanout = 1; REG Node = 'clk_out~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { temp[1] clk_out~reg0 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.399 ns ( 81.34 % ) " "Info: Total cell delay = 1.399 ns ( 81.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.321 ns ( 18.66 % ) " "Info: Total interconnect delay = 0.321 ns ( 18.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { temp[1] clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.720 ns" { temp[1] {} clk_out~reg0 {} } { 0.000ns 0.321ns } { 0.259ns 1.140ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.709 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.709 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 5 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.033 ns) + CELL(0.000 ns) 3.709 ns clk_out~reg0 2 REG LC6_7_C1 1 " "Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC6_7_C1; Fanout = 1; REG Node = 'clk_out~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.033 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.19 % ) " "Info: Total cell delay = 1.676 ns ( 45.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.033 ns ( 54.81 % ) " "Info: Total interconnect delay = 2.033 ns ( 54.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.709 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.709 ns" { clk {} clk~out0 {} clk_out~reg0 {} } { 0.000ns 0.000ns 2.033ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.709 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.709 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 5 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.033 ns) + CELL(0.000 ns) 3.709 ns temp\[1\] 2 REG LC5_7_C1 4 " "Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC5_7_C1; Fanout = 4; REG Node = 'temp\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.033 ns" { clk temp[1] } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.19 % ) " "Info: Total cell delay = 1.676 ns ( 45.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.033 ns ( 54.81 % ) " "Info: Total interconnect delay = 2.033 ns ( 54.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.709 ns" { clk temp[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.709 ns" { clk {} clk~out0 {} temp[1] {} } { 0.000ns 0.000ns 2.033ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.709 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.709 ns" { clk {} clk~out0 {} clk_out~reg0 {} } { 0.000ns 0.000ns 2.033ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.709 ns" { clk temp[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.709 ns" { clk {} clk~out0 {} temp[1] {} } { 0.000ns 0.000ns 2.033ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.167 ns + " "Info: + Micro setup delay of destination is 0.167 ns" {  } { { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { temp[1] clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.720 ns" { temp[1] {} clk_out~reg0 {} } { 0.000ns 0.321ns } { 0.259ns 1.140ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.709 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.709 ns" { clk {} clk~out0 {} clk_out~reg0 {} } { 0.000ns 0.000ns 2.033ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.709 ns" { clk temp[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.709 ns" { clk {} clk~out0 {} temp[1] {} } { 0.000ns 0.000ns 2.033ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { clk_out~reg0 {} } { 0.000ns } { 0.259ns } "" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_out clk_out~reg0 8.379 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_out\" through register \"clk_out~reg0\" is 8.379 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.709 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.709 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 5 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.033 ns) + CELL(0.000 ns) 3.709 ns clk_out~reg0 2 REG LC6_7_C1 1 " "Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC6_7_C1; Fanout = 1; REG Node = 'clk_out~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.033 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.19 % ) " "Info: Total cell delay = 1.676 ns ( 45.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.033 ns ( 54.81 % ) " "Info: Total interconnect delay = 2.033 ns ( 54.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.709 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.709 ns" { clk {} clk~out0 {} clk_out~reg0 {} } { 0.000ns 0.000ns 2.033ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.158 ns + Longest register pin " "Info: + Longest register to pin delay is 4.158 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns clk_out~reg0 1 REG LC6_7_C1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC6_7_C1; Fanout = 1; REG Node = 'clk_out~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.188 ns) + CELL(2.711 ns) 4.158 ns clk_out 2 PIN PIN_171 0 " "Info: 2: + IC(1.188 ns) + CELL(2.711 ns) = 4.158 ns; Loc. = PIN_171; Fanout = 0; PIN Node = 'clk_out'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.899 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "D:/altera/72/quartus/bin/Frequency1.vhd" "" { Text "D:/altera/72/quartus/bin/Frequency1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.970 ns ( 71.43 % ) " "Info: Total cell delay = 2.970 ns ( 71.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.188 ns ( 28.57 % ) " "Info: Total interconnect delay = 1.188 ns ( 28.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.158 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.158 ns" { clk_out~reg0 {} clk_out {} } { 0.000ns 1.188ns } { 0.259ns 2.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.709 ns" { clk clk_out~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.709 ns" { clk {} clk~out0 {} clk_out~reg0 {} } { 0.000ns 0.000ns 2.033ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.158 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.158 ns" { clk_out~reg0 {} clk_out {} } { 0.000ns 1.188ns } { 0.259ns 2.711ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 23:06:43 2009 " "Info: Processing ended: Mon May 11 23:06:43 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}