frequency1.map.rpt

vhdl语言编写的交通灯程序

; Allow register retiming to trade off Tsu/Tco with Fmax                                     ; On               ; On            ;
; Auto ROM Replacement                                                                       ; On               ; On            ;
; Auto RAM Replacement                                                                       ; On               ; On            ;
; Auto Shift Register Replacement                                                            ; Auto             ; Auto          ;
; Auto Clock Enable Replacement                                                              ; On               ; On            ;
; Auto Resource Sharing                                                                      ; Off              ; Off           ;
; Allow Any RAM Size For Recognition                                                         ; Off              ; Off           ;
; Allow Any ROM Size For Recognition                                                         ; Off              ; Off           ;
; Allow Any Shift Register Size For Recognition                                              ; Off              ; Off           ;
; Ignore translate_off and synthesis_off directives                                          ; Off              ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                                         ; On               ; On            ;
; Ignore Maximum Fan-Out Assignments                                                         ; Off              ; Off           ;
; Retiming Meta-Stability Register Sequence Length                                           ; 2                ; 2             ;
; HDL message level                                                                          ; Level2           ; Level2        ;
; Suppress Register Optimization Related Messages                                            ; Off              ; Off           ;
; Number of Removed Registers Reported in Synthesis Report                                   ; 100              ; 100           ;
; Block Design Naming                                                                        ; Auto             ; Auto          ;
+--------------------------------------------------------------------------------------------+------------------+---------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                ;
+-----------------------------------------+-----------------+-----------------+-----------------------------------------+
; File Name with User-Entered Path        ; Used in Netlist ; File Type       ; File Name with Absolute Path            ;
+-----------------------------------------+-----------------+-----------------+-----------------------------------------+
; D:/altera/72/quartus/bin/Frequency1.vhd ; yes             ; User VHDL File  ; D:/altera/72/quartus/bin/Frequency1.vhd ;
+-----------------------------------------+-----------------+-----------------+-----------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+--------------------------------+------------+
; Resource                       ; Usage      ;
+--------------------------------+------------+
; Total logic elements           ; 5          ;
; Total combinational functions  ; 5          ;
;     -- Total 4-input functions ; 3          ;
;     -- Total 3-input functions ; 1          ;
;     -- Total 2-input functions ; 0          ;
;     -- Total 1-input functions ; 1          ;
;     -- Total 0-input functions ; 0          ;
; Total registers                ; 5          ;
; I/O pins                       ; 2          ;
; Maximum fan-out node           ; temp[0]    ;
; Maximum fan-out                ; 5          ;
; Total fan-out                  ; 22         ;
; Average fan-out                ; 3.14       ;
+--------------------------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |Frequency1                ; 5 (5)       ; 5            ; 0           ; 2    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; 0 (0)      ; |Frequency1         ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 11 23:06:29 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Frequency1 -c Frequency1
Info: Found 2 design units, including 1 entities, in source file D:/altera/72/quartus/bin/Frequency1.vhd
    Info: Found design unit 1: Frequency1-Frequency1_arc
    Info: Found entity 1: Frequency1
Info: Elaborating entity "Frequency1" for the top level hierarchy
Info: Implemented 7 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 5 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 158 megabytes of memory during processing
    Info: Processing ended: Mon May 11 23:06:31 2009
    Info: Elapsed time: 00:00:02