frequency1.tan.rpt

vhdl语言编写的交通灯程序

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                          ;
+-------+------------------------------------------------+---------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From    ; To           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[1] ; clk_out~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[1] ; temp[3]      ; clk        ; clk      ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[1] ; temp[1]      ; clk        ; clk      ; None                        ; None                      ; 1.720 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[0] ; clk_out~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.689 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[0] ; temp[3]      ; clk        ; clk      ; None                        ; None                      ; 1.689 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[0] ; temp[1]      ; clk        ; clk      ; None                        ; None                      ; 1.689 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[1] ; temp[2]      ; clk        ; clk      ; None                        ; None                      ; 1.621 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[2] ; clk_out~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.582 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[2] ; temp[3]      ; clk        ; clk      ; None                        ; None                      ; 1.582 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[2] ; temp[2]      ; clk        ; clk      ; None                        ; None                      ; 1.582 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[2] ; temp[1]      ; clk        ; clk      ; None                        ; None                      ; 1.582 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[0] ; temp[2]      ; clk        ; clk      ; None                        ; None                      ; 0.854 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[0] ; temp[0]      ; clk        ; clk      ; None                        ; None                      ; 0.854 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[3] ; clk_out~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[3] ; temp[3]      ; clk        ; clk      ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; Restricted to 233.70 MHz ( period = 4.279 ns ) ; temp[3] ; temp[1]      ; clk        ; clk      ; None                        ; None                      ; 0.820 ns                ;
+-------+------------------------------------------------+---------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 8.379 ns   ; clk_out~reg0 ; clk_out ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 11 23:06:42 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Frequency1 -c Frequency1
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 233.7 MHz between source register "temp[1]" and destination register "clk_out~reg0"
    Info: fmax restricted to clock pin edge rate 4.279 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.720 ns
            Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC5_7_C1; Fanout = 4; REG Node = 'temp[1]'
            Info: 2: + IC(0.321 ns) + CELL(1.140 ns) = 1.720 ns; Loc. = LC6_7_C1; Fanout = 1; REG Node = 'clk_out~reg0'
            Info: Total cell delay = 1.399 ns ( 81.34 % )
            Info: Total interconnect delay = 0.321 ns ( 18.66 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.709 ns
                Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC6_7_C1; Fanout = 1; REG Node = 'clk_out~reg0'
                Info: Total cell delay = 1.676 ns ( 45.19 % )
                Info: Total interconnect delay = 2.033 ns ( 54.81 % )
            Info: - Longest clock path from clock "clk" to source register is 3.709 ns
                Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC5_7_C1; Fanout = 4; REG Node = 'temp[1]'
                Info: Total cell delay = 1.676 ns ( 45.19 % )
                Info: Total interconnect delay = 2.033 ns ( 54.81 % )
        Info: + Micro clock to output delay of source is 0.512 ns
        Info: + Micro setup delay of destination is 0.167 ns
Info: tco from clock "clk" to destination pin "clk_out" through register "clk_out~reg0" is 8.379 ns
    Info: + Longest clock path from clock "clk" to source register is 3.709 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(2.033 ns) + CELL(0.000 ns) = 3.709 ns; Loc. = LC6_7_C1; Fanout = 1; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 1.676 ns ( 45.19 % )
        Info: Total interconnect delay = 2.033 ns ( 54.81 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Longest register to pin delay is 4.158 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC6_7_C1; Fanout = 1; REG Node = 'clk_out~reg0'
        Info: 2: + IC(1.188 ns) + CELL(2.711 ns) = 4.158 ns; Loc. = PIN_171; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 2.970 ns ( 71.43 % )
        Info: Total interconnect delay = 1.188 ns ( 28.57 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Mon May 11 23:06:43 2009
    Info: Elapsed time: 00:00:01