statusselect.tan.rpt

vhdl语言编写的交通灯程序

; N/A           ; None        ; -4.719 ns ; show ; t[6]       ; clk      ;
; N/A           ; None        ; -4.720 ns ; show ; t[9]       ; clk      ;
; N/A           ; None        ; -4.720 ns ; show ; t[11]      ; clk      ;
; N/A           ; None        ; -4.787 ns ; show ; t[16]      ; clk      ;
; N/A           ; None        ; -4.790 ns ; show ; t[18]      ; clk      ;
; N/A           ; None        ; -5.456 ns ; show ; temp[0]    ; clk      ;
; N/A           ; None        ; -5.456 ns ; show ; temp[1]    ; clk      ;
+---------------+-------------+-----------+------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 11 23:49:04 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off StatusSelect -c StatusSelect
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 114.08 MHz between source register "t[0]" and destination register "t[17]" (period= 8.766 ns)
    Info: + Longest register to register delay is 8.087 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC1_7_F2; Fanout = 3; REG Node = 't[0]'
        Info: 2: + IC(0.290 ns) + CELL(1.798 ns) = 2.347 ns; Loc. = LC2_7_F2; Fanout = 2; COMB Node = 'Add0~266'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 2.502 ns; Loc. = LC3_7_F2; Fanout = 2; COMB Node = 'Add0~269'
        Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 2.657 ns; Loc. = LC4_7_F2; Fanout = 2; COMB Node = 'Add0~272'
        Info: 5: + IC(0.000 ns) + CELL(0.155 ns) = 2.812 ns; Loc. = LC5_7_F2; Fanout = 2; COMB Node = 'Add0~275'
        Info: 6: + IC(0.000 ns) + CELL(0.155 ns) = 2.967 ns; Loc. = LC6_7_F2; Fanout = 2; COMB Node = 'Add0~278'
        Info: 7: + IC(0.000 ns) + CELL(0.155 ns) = 3.122 ns; Loc. = LC7_7_F2; Fanout = 2; COMB Node = 'Add0~281'
        Info: 8: + IC(0.000 ns) + CELL(0.155 ns) = 3.277 ns; Loc. = LC8_7_F2; Fanout = 2; COMB Node = 'Add0~284'
        Info: 9: + IC(0.000 ns) + CELL(0.155 ns) = 3.432 ns; Loc. = LC9_7_F2; Fanout = 2; COMB Node = 'Add0~287'
        Info: 10: + IC(0.000 ns) + CELL(0.155 ns) = 3.587 ns; Loc. = LC10_7_F2; Fanout = 2; COMB Node = 'Add0~290'
        Info: 11: + IC(0.778 ns) + CELL(0.155 ns) = 4.520 ns; Loc. = LC1_9_F2; Fanout = 2; COMB Node = 'Add0~293'
        Info: 12: + IC(0.000 ns) + CELL(0.155 ns) = 4.675 ns; Loc. = LC2_9_F2; Fanout = 2; COMB Node = 'Add0~296'
        Info: 13: + IC(0.000 ns) + CELL(0.155 ns) = 4.830 ns; Loc. = LC3_9_F2; Fanout = 2; COMB Node = 'Add0~299'
        Info: 14: + IC(0.000 ns) + CELL(0.155 ns) = 4.985 ns; Loc. = LC4_9_F2; Fanout = 2; COMB Node = 'Add0~308'
        Info: 15: + IC(0.000 ns) + CELL(0.155 ns) = 5.140 ns; Loc. = LC5_9_F2; Fanout = 2; COMB Node = 'Add0~302'
        Info: 16: + IC(0.000 ns) + CELL(0.155 ns) = 5.295 ns; Loc. = LC6_9_F2; Fanout = 2; COMB Node = 'Add0~311'
        Info: 17: + IC(0.000 ns) + CELL(0.155 ns) = 5.450 ns; Loc. = LC7_9_F2; Fanout = 2; COMB Node = 'Add0~305'
        Info: 18: + IC(0.000 ns) + CELL(0.155 ns) = 5.605 ns; Loc. = LC8_9_F2; Fanout = 2; COMB Node = 'Add0~314'
        Info: 19: + IC(0.000 ns) + CELL(1.020 ns) = 6.625 ns; Loc. = LC9_9_F2; Fanout = 1; COMB Node = 'Add0~316'
        Info: 20: + IC(1.194 ns) + CELL(0.268 ns) = 8.087 ns; Loc. = LC5_5_F2; Fanout = 3; REG Node = 't[17]'
        Info: Total cell delay = 5.825 ns ( 72.03 % )
        Info: Total interconnect delay = 2.262 ns ( 27.97 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.703 ns
            Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(2.027 ns) + CELL(0.000 ns) = 3.703 ns; Loc. = LC5_5_F2; Fanout = 3; REG Node = 't[17]'
            Info: Total cell delay = 1.676 ns ( 45.26 % )
            Info: Total interconnect delay = 2.027 ns ( 54.74 % )
        Info: - Longest clock path from clock "clk" to source register is 3.703 ns
            Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'
            Info: 2: + IC(2.027 ns) + CELL(0.000 ns) = 3.703 ns; Loc. = LC1_7_F2; Fanout = 3; REG Node = 't[0]'
            Info: Total cell delay = 1.676 ns ( 45.26 % )
            Info: Total interconnect delay = 2.027 ns ( 54.74 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Micro setup delay of destination is 0.167 ns
Info: tsu for register "temp[0]" (data pin = "show", clock pin = "clk") is 5.999 ns
    Info: + Longest pin to register delay is 9.535 ns
        Info: 1: + IC(0.000 ns) + CELL(2.148 ns) = 2.148 ns; Loc. = PIN_207; Fanout = 23; PIN Node = 'show'
        Info: 2: + IC(5.523 ns) + CELL(1.278 ns) = 8.949 ns; Loc. = LC1_4_F2; Fanout = 2; COMB Node = 'temp~106'
        Info: 3: + IC(0.318 ns) + CELL(0.268 ns) = 9.535 ns; Loc. = LC6_4_F2; Fanout = 3; REG Node = 'temp[0]'
        Info: Total cell delay = 3.694 ns ( 38.74 % )
        Info: Total interconnect delay = 5.841 ns ( 61.26 % )
    Info: + Micro setup delay of destination is 0.167 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.703 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(2.027 ns) + CELL(0.000 ns) = 3.703 ns; Loc. = LC6_4_F2; Fanout = 3; REG Node = 'temp[0]'
        Info: Total cell delay = 1.676 ns ( 45.26 % )
        Info: Total interconnect delay = 2.027 ns ( 54.74 % )
Info: tco from clock "clk" to destination pin "sel[2]" through register "temp[2]" is 11.610 ns
    Info: + Longest clock path from clock "clk" to source register is 3.703 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(2.027 ns) + CELL(0.000 ns) = 3.703 ns; Loc. = LC9_4_F2; Fanout = 3; REG Node = 'temp[2]'
        Info: Total cell delay = 1.676 ns ( 45.26 % )
        Info: Total interconnect delay = 2.027 ns ( 54.74 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Longest register to pin delay is 7.395 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC9_4_F2; Fanout = 3; REG Node = 'temp[2]'
        Info: 2: + IC(4.425 ns) + CELL(2.711 ns) = 7.395 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'sel[2]'
        Info: Total cell delay = 2.970 ns ( 40.16 % )
        Info: Total interconnect delay = 4.425 ns ( 59.84 % )
Info: th for register "a" (data pin = "show", clock pin = "clk") is -4.454 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.703 ns
        Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'
        I