statusselect.tan.qmsg

vhdl语言编写的交通灯程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk sel\[2\] temp\[2\] 11.610 ns register " "Info: tco from clock \"clk\" to destination pin \"sel\[2\]\" through register \"temp\[2\]\" is 11.610 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.703 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 24 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.027 ns) + CELL(0.000 ns) 3.703 ns temp\[2\] 2 REG LC9_4_F2 3 " "Info: 2: + IC(2.027 ns) + CELL(0.000 ns) = 3.703 ns; Loc. = LC9_4_F2; Fanout = 3; REG Node = 'temp\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.027 ns" { clk temp[2] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.26 % ) " "Info: Total cell delay = 1.676 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.027 ns ( 54.74 % ) " "Info: Total interconnect delay = 2.027 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk temp[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} temp[2] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.395 ns + Longest register pin " "Info: + Longest register to pin delay is 7.395 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns temp\[2\] 1 REG LC9_4_F2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC9_4_F2; Fanout = 3; REG Node = 'temp\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp[2] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.425 ns) + CELL(2.711 ns) 7.395 ns sel\[2\] 2 PIN PIN_17 0 " "Info: 2: + IC(4.425 ns) + CELL(2.711 ns) = 7.395 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'sel\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.136 ns" { temp[2] sel[2] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.970 ns ( 40.16 % ) " "Info: Total cell delay = 2.970 ns ( 40.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.425 ns ( 59.84 % ) " "Info: Total interconnect delay = 4.425 ns ( 59.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.395 ns" { temp[2] sel[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.395 ns" { temp[2] {} sel[2] {} } { 0.000ns 4.425ns } { 0.259ns 2.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk temp[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} temp[2] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.395 ns" { temp[2] sel[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.395 ns" { temp[2] {} sel[2] {} } { 0.000ns 4.425ns } { 0.259ns 2.711ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "a show clk -4.454 ns register " "Info: th for register \"a\" (data pin = \"show\", clock pin = \"clk\") is -4.454 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.703 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 24 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.027 ns) + CELL(0.000 ns) 3.703 ns a 2 REG LC3_4_F2 4 " "Info: 2: + IC(2.027 ns) + CELL(0.000 ns) = 3.703 ns; Loc. = LC3_4_F2; Fanout = 4; REG Node = 'a'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.027 ns" { clk a } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.26 % ) " "Info: Total cell delay = 1.676 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.027 ns ( 54.74 % ) " "Info: Total interconnect delay = 2.027 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk a } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} a {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.376 ns + " "Info: + Micro hold delay of destination is 0.376 ns" {  } { { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.533 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.148 ns) 2.148 ns show 1 PIN PIN_207 23 " "Info: 1: + IC(0.000 ns) + CELL(2.148 ns) = 2.148 ns; Loc. = PIN_207; Fanout = 23; PIN Node = 'show'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { show } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.570 ns) + CELL(0.815 ns) 8.533 ns a 2 REG LC3_4_F2 4 " "Info: 2: + IC(5.570 ns) + CELL(0.815 ns) = 8.533 ns; Loc. = LC3_4_F2; Fanout = 4; REG Node = 'a'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.385 ns" { show a } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.963 ns ( 34.72 % ) " "Info: Total cell delay = 2.963 ns ( 34.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.570 ns ( 65.28 % ) " "Info: Total interconnect delay = 5.570 ns ( 65.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.533 ns" { show a } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.533 ns" { show {} show~out0 {} a {} } { 0.000ns 0.000ns 5.570ns } { 0.000ns 2.148ns 0.815ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk a } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} a {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.533 ns" { show a } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.533 ns" { show {} show~out0 {} a {} } { 0.000ns 0.000ns 5.570ns } { 0.000ns 2.148ns 0.815ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 23:49:06 2009 " "Info: Processing ended: Mon May 11 23:49:06 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}