statusselect.tan.qmsg

vhdl语言编写的交通灯程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 6 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register t\[0\] register t\[17\] 114.08 MHz 8.766 ns Internal " "Info: Clock \"clk\" has Internal fmax of 114.08 MHz between source register \"t\[0\]\" and destination register \"t\[17\]\" (period= 8.766 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.087 ns + Longest register register " "Info: + Longest register to register delay is 8.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns t\[0\] 1 REG LC1_7_F2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC1_7_F2; Fanout = 3; REG Node = 't\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { t[0] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(1.798 ns) 2.347 ns Add0~266 2 COMB LC2_7_F2 2 " "Info: 2: + IC(0.290 ns) + CELL(1.798 ns) = 2.347 ns; Loc. = LC2_7_F2; Fanout = 2; COMB Node = 'Add0~266'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.088 ns" { t[0] Add0~266 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.502 ns Add0~269 3 COMB LC3_7_F2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 2.502 ns; Loc. = LC3_7_F2; Fanout = 2; COMB Node = 'Add0~269'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~266 Add0~269 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.657 ns Add0~272 4 COMB LC4_7_F2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 2.657 ns; Loc. = LC4_7_F2; Fanout = 2; COMB Node = 'Add0~272'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~269 Add0~272 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.812 ns Add0~275 5 COMB LC5_7_F2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.155 ns) = 2.812 ns; Loc. = LC5_7_F2; Fanout = 2; COMB Node = 'Add0~275'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~272 Add0~275 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.967 ns Add0~278 6 COMB LC6_7_F2 2 " "Info: 6: + IC(0.000 ns) + CELL(0.155 ns) = 2.967 ns; Loc. = LC6_7_F2; Fanout = 2; COMB Node = 'Add0~278'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~275 Add0~278 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 3.122 ns Add0~281 7 COMB LC7_7_F2 2 " "Info: 7: + IC(0.000 ns) + CELL(0.155 ns) = 3.122 ns; Loc. = LC7_7_F2; Fanout = 2; COMB Node = 'Add0~281'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~278 Add0~281 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 3.277 ns Add0~284 8 COMB LC8_7_F2 2 " "Info: 8: + IC(0.000 ns) + CELL(0.155 ns) = 3.277 ns; Loc. = LC8_7_F2; Fanout = 2; COMB Node = 'Add0~284'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~281 Add0~284 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 3.432 ns Add0~287 9 COMB LC9_7_F2 2 " "Info: 9: + IC(0.000 ns) + CELL(0.155 ns) = 3.432 ns; Loc. = LC9_7_F2; Fanout = 2; COMB Node = 'Add0~287'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~284 Add0~287 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 3.587 ns Add0~290 10 COMB LC10_7_F2 2 " "Info: 10: + IC(0.000 ns) + CELL(0.155 ns) = 3.587 ns; Loc. = LC10_7_F2; Fanout = 2; COMB Node = 'Add0~290'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~287 Add0~290 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.155 ns) 4.520 ns Add0~293 11 COMB LC1_9_F2 2 " "Info: 11: + IC(0.778 ns) + CELL(0.155 ns) = 4.520 ns; Loc. = LC1_9_F2; Fanout = 2; COMB Node = 'Add0~293'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.933 ns" { Add0~290 Add0~293 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.675 ns Add0~296 12 COMB LC2_9_F2 2 " "Info: 12: + IC(0.000 ns) + CELL(0.155 ns) = 4.675 ns; Loc. = LC2_9_F2; Fanout = 2; COMB Node = 'Add0~296'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~293 Add0~296 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.830 ns Add0~299 13 COMB LC3_9_F2 2 " "Info: 13: + IC(0.000 ns) + CELL(0.155 ns) = 4.830 ns; Loc. = LC3_9_F2; Fanout = 2; COMB Node = 'Add0~299'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~296 Add0~299 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.985 ns Add0~308 14 COMB LC4_9_F2 2 " "Info: 14: + IC(0.000 ns) + CELL(0.155 ns) = 4.985 ns; Loc. = LC4_9_F2; Fanout = 2; COMB Node = 'Add0~308'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~299 Add0~308 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.140 ns Add0~302 15 COMB LC5_9_F2 2 " "Info: 15: + IC(0.000 ns) + CELL(0.155 ns) = 5.140 ns; Loc. = LC5_9_F2; Fanout = 2; COMB Node = 'Add0~302'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~308 Add0~302 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.295 ns Add0~311 16 COMB LC6_9_F2 2 " "Info: 16: + IC(0.000 ns) + CELL(0.155 ns) = 5.295 ns; Loc. = LC6_9_F2; Fanout = 2; COMB Node = 'Add0~311'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~302 Add0~311 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.450 ns Add0~305 17 COMB LC7_9_F2 2 " "Info: 17: + IC(0.000 ns) + CELL(0.155 ns) = 5.450 ns; Loc. = LC7_9_F2; Fanout = 2; COMB Node = 'Add0~305'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~311 Add0~305 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.605 ns Add0~314 18 COMB LC8_9_F2 2 " "Info: 18: + IC(0.000 ns) + CELL(0.155 ns) = 5.605 ns; Loc. = LC8_9_F2; Fanout = 2; COMB Node = 'Add0~314'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Add0~305 Add0~314 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 6.625 ns Add0~316 19 COMB LC9_9_F2 1 " "Info: 19: + IC(0.000 ns) + CELL(1.020 ns) = 6.625 ns; Loc. = LC9_9_F2; Fanout = 1; COMB Node = 'Add0~316'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.020 ns" { Add0~314 Add0~316 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.268 ns) 8.087 ns t\[17\] 20 REG LC5_5_F2 3 " "Info: 20: + IC(1.194 ns) + CELL(0.268 ns) = 8.087 ns; Loc. = LC5_5_F2; Fanout = 3; REG Node = 't\[17\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { Add0~316 t[17] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.825 ns ( 72.03 % ) " "Info: Total cell delay = 5.825 ns ( 72.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.262 ns ( 27.97 % ) " "Info: Total interconnect delay = 2.262 ns ( 27.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.087 ns" { t[0] Add0~266 Add0~269 Add0~272 Add0~275 Add0~278 Add0~281 Add0~284 Add0~287 Add0~290 Add0~293 Add0~296 Add0~299 Add0~308 Add0~302 Add0~311 Add0~305 Add0~314 Add0~316 t[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.087 ns" { t[0] {} Add0~266 {} Add0~269 {} Add0~272 {} Add0~275 {} Add0~278 {} Add0~281 {} Add0~284 {} Add0~287 {} Add0~290 {} Add0~293 {} Add0~296 {} Add0~299 {} Add0~308 {} Add0~302 {} Add0~311 {} Add0~305 {} Add0~314 {} Add0~316 {} t[17] {} } { 0.000ns 0.290ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.778ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.194ns } { 0.259ns 1.798ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 1.020ns 0.268ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.703 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 24 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.027 ns) + CELL(0.000 ns) 3.703 ns t\[17\] 2 REG LC5_5_F2 3 " "Info: 2: + IC(2.027 ns) + CELL(0.000 ns) = 3.703 ns; Loc. = LC5_5_F2; Fanout = 3; REG Node = 't\[17\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.027 ns" { clk t[17] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.26 % ) " "Info: Total cell delay = 1.676 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.027 ns ( 54.74 % ) " "Info: Total interconnect delay = 2.027 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk t[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} t[17] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.703 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 24 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.027 ns) + CELL(0.000 ns) 3.703 ns t\[0\] 2 REG LC1_7_F2 3 " "Info: 2: + IC(2.027 ns) + CELL(0.000 ns) = 3.703 ns; Loc. = LC1_7_F2; Fanout = 3; REG Node = 't\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.027 ns" { clk t[0] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.26 % ) " "Info: Total cell delay = 1.676 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.027 ns ( 54.74 % ) " "Info: Total interconnect delay = 2.027 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk t[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} t[0] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk t[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} t[17] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk t[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} t[0] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.167 ns + " "Info: + Micro setup delay of destination is 0.167 ns" {  } { { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.087 ns" { t[0] Add0~266 Add0~269 Add0~272 Add0~275 Add0~278 Add0~281 Add0~284 Add0~287 Add0~290 Add0~293 Add0~296 Add0~299 Add0~308 Add0~302 Add0~311 Add0~305 Add0~314 Add0~316 t[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.087 ns" { t[0] {} Add0~266 {} Add0~269 {} Add0~272 {} Add0~275 {} Add0~278 {} Add0~281 {} Add0~284 {} Add0~287 {} Add0~290 {} Add0~293 {} Add0~296 {} Add0~299 {} Add0~308 {} Add0~302 {} Add0~311 {} Add0~305 {} Add0~314 {} Add0~316 {} t[17] {} } { 0.000ns 0.290ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.778ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.194ns } { 0.259ns 1.798ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 0.155ns 1.020ns 0.268ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk t[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} t[17] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk t[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} t[0] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "temp\[0\] show clk 5.999 ns register " "Info: tsu for register \"temp\[0\]\" (data pin = \"show\", clock pin = \"clk\") is 5.999 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.535 ns + Longest pin register " "Info: + Longest pin to register delay is 9.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.148 ns) 2.148 ns show 1 PIN PIN_207 23 " "Info: 1: + IC(0.000 ns) + CELL(2.148 ns) = 2.148 ns; Loc. = PIN_207; Fanout = 23; PIN Node = 'show'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { show } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.523 ns) + CELL(1.278 ns) 8.949 ns temp~106 2 COMB LC1_4_F2 2 " "Info: 2: + IC(5.523 ns) + CELL(1.278 ns) = 8.949 ns; Loc. = LC1_4_F2; Fanout = 2; COMB Node = 'temp~106'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.801 ns" { show temp~106 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.268 ns) 9.535 ns temp\[0\] 3 REG LC6_4_F2 3 " "Info: 3: + IC(0.318 ns) + CELL(0.268 ns) = 9.535 ns; Loc. = LC6_4_F2; Fanout = 3; REG Node = 'temp\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.586 ns" { temp~106 temp[0] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.694 ns ( 38.74 % ) " "Info: Total cell delay = 3.694 ns ( 38.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.841 ns ( 61.26 % ) " "Info: Total interconnect delay = 5.841 ns ( 61.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.535 ns" { show temp~106 temp[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.535 ns" { show {} show~out0 {} temp~106 {} temp[0] {} } { 0.000ns 0.000ns 5.523ns 0.318ns } { 0.000ns 2.148ns 1.278ns 0.268ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.167 ns + " "Info: + Micro setup delay of destination is 0.167 ns" {  } { { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.703 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.676 ns) 1.676 ns clk 1 CLK PIN_154 24 " "Info: 1: + IC(0.000 ns) + CELL(1.676 ns) = 1.676 ns; Loc. = PIN_154; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.027 ns) + CELL(0.000 ns) 3.703 ns temp\[0\] 2 REG LC6_4_F2 3 " "Info: 2: + IC(2.027 ns) + CELL(0.000 ns) = 3.703 ns; Loc. = LC6_4_F2; Fanout = 3; REG Node = 'temp\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.027 ns" { clk temp[0] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.676 ns ( 45.26 % ) " "Info: Total cell delay = 1.676 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.027 ns ( 54.74 % ) " "Info: Total interconnect delay = 2.027 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk temp[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} temp[0] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.535 ns" { show temp~106 temp[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.535 ns" { show {} show~out0 {} temp~106 {} temp[0] {} } { 0.000ns 0.000ns 5.523ns 0.318ns } { 0.000ns 2.148ns 1.278ns 0.268ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { clk temp[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.703 ns" { clk {} clk~out0 {} temp[0] {} } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.676ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}