prev_cmp_statusselect.qmsg

vhdl语言编写的交通灯程序

{ "Info" "IMPP_MPP_USER_DEVICE" "StatusSelect EP20K300EQC240-3 " "Info: Selected device EP20K300EQC240-3 for design \"StatusSelect\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "clk automatically " "Info: Promoted cell \"clk\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0 "" 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Mon May 11 2009 23:48:54 " "Info: Started fitting attempt 1 on Mon May 11 2009 at 23:48:54" {  } {  } 0 0 "Started fitting attempt %1!d! on %2!s! at %3!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "0 " "Info: Overall column FastTrack interconnect = 0%" {  } {  } 0 0 "Overall column FastTrack interconnect = %1!d!%%" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "0 " "Info: Overall row FastTrack interconnect = 0%" {  } {  } 0 0 "Overall row FastTrack interconnect = %1!d!%%" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "0 " "Info: Maximum column FastTrack interconnect = 0%" {  } {  } 0 0 "Maximum column FastTrack interconnect = %1!d!%%" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "3 " "Info: Maximum row FastTrack interconnect = 3%" {  } {  } 0 0 "Maximum row FastTrack interconnect = %1!d!%%" 0 0 "" 0}  } {  } 0 0 "Design requires the following device routing resources:" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.108 ns register register " "Info: Estimated most critical path is register to register delay of 9.108 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns t\[11\] 1 REG LAB_8_F2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LAB_8_F2; Fanout = 3; REG Node = 't\[11\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { t[11] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(1.428 ns) 1.946 ns Equal0~183 2 COMB LAB_8_F2 1 " "Info: 2: + IC(0.259 ns) + CELL(1.428 ns) = 1.946 ns; Loc. = LAB_8_F2; Fanout = 1; COMB Node = 'Equal0~183'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.687 ns" { t[11] Equal0~183 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.961 ns) + CELL(1.428 ns) 4.335 ns Equal0~185 3 COMB LAB_5_F2 1 " "Info: 3: + IC(0.961 ns) + CELL(1.428 ns) = 4.335 ns; Loc. = LAB_5_F2; Fanout = 1; COMB Node = 'Equal0~185'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.389 ns" { Equal0~183 Equal0~185 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(1.428 ns) 6.022 ns Equal0~186 4 COMB LAB_5_F2 10 " "Info: 4: + IC(0.259 ns) + CELL(1.428 ns) = 6.022 ns; Loc. = LAB_5_F2; Fanout = 10; COMB Node = 'Equal0~186'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.687 ns" { Equal0~185 Equal0~186 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(1.428 ns) 7.709 ns temp~106 5 COMB LAB_4_F2 2 " "Info: 5: + IC(0.259 ns) + CELL(1.428 ns) = 7.709 ns; Loc. = LAB_4_F2; Fanout = 2; COMB Node = 'temp~106'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.687 ns" { Equal0~186 temp~106 } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(1.140 ns) 9.108 ns temp\[0\] 6 REG LAB_4_F2 3 " "Info: 6: + IC(0.259 ns) + CELL(1.140 ns) = 9.108 ns; Loc. = LAB_4_F2; Fanout = 3; REG Node = 'temp\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.399 ns" { temp~106 temp[0] } "NODE_NAME" } } { "StatusSelect.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL实现的交通灯程序/trafficlightvhdlcode/6v/m6/StatusSelect.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.111 ns ( 78.07 % ) " "Info: Total cell delay = 7.111 ns ( 78.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.997 ns ( 21.93 % ) " "Info: Total interconnect delay = 1.997 ns ( 21.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.108 ns" { t[11] Equal0~183 Equal0~185 Equal0~186 temp~106 temp[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}