📄 statusselect.fit.rpt
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Fitter report for StatusSelect
Mon May 11 23:49:00 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Input Pins
6. Output Pins
7. All Package Pins
8. Control Signals
9. Global & Other Fast Signals
10. Carry Chains
11. Non-Global High Fan-Out Signals
12. Local Routing Interconnect
13. MegaLAB Interconnect
14. LAB External Interconnect
15. MegaLAB Usage Summary
16. Row Interconnect
17. LAB Column Interconnect
18. ESB Column Interconnect
19. Fitter Resource Usage Summary
20. Fitter Resource Utilization by Entity
21. Delay Chain Summary
22. I/O Bank Usage
23. Pin-Out File
24. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Mon May 11 23:49:00 2009 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; StatusSelect ;
; Top-level Entity Name ; StatusSelect ;
; Family ; APEX20KE ;
; Device ; EP20K300EQC240-3 ;
; Timing Models ; Final ;
; Total logic elements ; 50 / 11,520 ( < 1 % ) ;
; Total pins ; 6 / 152 ( 4 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 147,456 ( 0 % ) ;
; Total PLLs ; 0 ;
+-----------------------+------------------------------------------+
+------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------+--------------------+--------------------+
; Device ; EP20K300EQC240-3 ; ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Turbo Bit ; On ; On ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Auto Global Clock ; On ; On ;
; Auto Global Output Enable ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; SignalProbe signals routed during normal compilation ; Off ; Off ;
+------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; nWS, nRS, nCS, CS ; Unreserved ;
; RDYnBUSY ; Unreserved ;
; Data[7..1] ; Unreserved ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+-------------+--------------+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+----------------------+--------------+
; Name ; Pin # ; MegaLAB Row ; MegaLAB Col. ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; PCI I/O Enabled ; Single-Pin CE ; FastRow Interconnect ; I/O Standard ;
+------+-------+-------------+--------------+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+----------------------+--------------+
; show ; 207 ; -- ; 2 ; 2 ; 23 ; no ; no ; no ; no ; no ; no ; no ; 3.3-V LVTTL ;
; clk ; 154 ; -- ; -- ; -- ; 24 ; yes ; no ; no ; no ; no ; no ; no ; 3.3-V LVTTL ;
+------+-------+-------------+--------------+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+----------------------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+--------+-------+-------------+--------------+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
; Name ; Pin # ; MegaLAB Row ; MegaLAB Col. ; Col. ; I/O Register ; Use Local Routing Output ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Single-Pin OE ; Single-Pin CE ; Open Drain ; TRI Primitive ; I/O Standard ;
+--------+-------+-------------+--------------+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
; sel[0] ; 195 ; -- ; 2 ; 16 ; no ; no ; no ; no ; no ; no ; no ; no ; no ; 3.3-V LVTTL ;
; sel[1] ; 163 ; F ; -- ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; 3.3-V LVTTL ;
; sel[2] ; 17 ; F ; -- ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; 3.3-V LVTTL ;
; voice ; 164 ; F ; -- ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; 3.3-V LVTTL ;
+--------+-------+-------------+--------------+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
+-----------------------------------+
; All Package Pins ;
+-------+------------+--------------+
; Pin # ; Usage ; I/O Standard ;
+-------+------------+--------------+
; 1 ; VCC_INT ; ;
; 2 ; GND* ; ;
; 3 ; GND* ; ;
; 4 ; GND* ; ;
; 5 ; VCC_INT ; ;
; 6 ; GND ; ;
; 7 ; GND* ; ;
; 8 ; GND* ; ;
; 9 ; GND* ; ;
; 10 ; GND* ; ;
; 11 ; GND* ; ;
; 12 ; VCC_IO ; ;
; 13 ; GND* ; ;
; 14 ; VCC_INT ; ;
; 15 ; GND ; ;
; 16 ; GND* ; ;
; 17 ; sel[2] ; 3.3-V LVTTL ;
; 18 ; GND* ; ;
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