ddsc.hif

DDS数字频率合成器

Version 6.1 Build 201 11/27/2006 SJ Full Version
11
850
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
H:|edasoftware|megcore|fir_compiler-v3.1.0|lib|
H:|edasoftware|megcore|nco-v2.2.1|lib|
H:|edasoftware|megcore|fir_compiler-v3.2.0|lib|
H:|edasoftware|megcore|nco-v2.3.0|lib|
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
ddsc
# storage
db|ddsc.(0).cnf
db|ddsc.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
ddsc.vhd
96fdb376aa2792cbd5911768e7f3dd18
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
freq_width
32
PARAMETER_SIGNED_DEC
DEF
phase_width
12
PARAMETER_SIGNED_DEC
DEF
adder_width
32
PARAMETER_SIGNED_DEC
DEF
romad_width
10
PARAMETER_SIGNED_DEC
DEF
rom_d_width
10
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
|
}
# end
# entity
LPM_ROM
# storage
db|ddsc.(1).cnf
db|ddsc.(1).cnf
# case_insensitive
# source_file
..|..|altera|61|quartus|libraries|megafunctions|LPM_ROM.tdf
7591f710cf1ef68e11f5368e27b1ba5
6
# user_parameter {
LPM_WIDTH
10
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHAD
10
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
0
PARAMETER_SIGNED_DEC
USR
LPM_ADDRESS_CONTROL
UNREGISTERED
PARAMETER_UNKNOWN
USR
LPM_OUTDATA
REGISTERED
PARAMETER_UNKNOWN
USR
LPM_FILE
sin_rom.mif
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
Q9
-1
3
Q8
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
OUTCLOCK
-1
3
ADDRESS9
-1
3
ADDRESS8
-1
3
ADDRESS7
-1
3
ADDRESS6
-1
3
ADDRESS5
-1
3
ADDRESS4
-1
3
ADDRESS3
-1
3
ADDRESS2
-1
3
ADDRESS1
-1
3
ADDRESS0
-1
3
}
# include_file {
..|..|altera|61|quartus|libraries|megafunctions|aglobal61.inc
b513fb574ceb8f5886cd4ba429e82ec
..|..|altera|61|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
}
# hierarchies {
lpm_rom:i_rom
}
# end
# entity
altrom
# storage
db|ddsc.(2).cnf
db|ddsc.(2).cnf
# case_insensitive
# source_file
..|..|altera|61|quartus|libraries|megafunctions|altrom.tdf
1579604c75834e7b8dab751e49ba8a2
6
# user_parameter {
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
WIDTH
10
PARAMETER_UNKNOWN
USR
AD_WIDTH
10
PARAMETER_UNKNOWN
USR
NUMWORDS
1024
PARAMETER_UNKNOWN
USR
FILE
sin_rom.mif
PARAMETER_UNKNOWN
USR
REGISTERINPUTMODE
DEFAULT
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
2048
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clocko
-1
3
address9
-1
3
address8
-1
3
address7
-1
3
address6
-1
3
address5
-1
3
address4
-1
3
address3
-1
3
address2
-1
3
address1
-1
3
address0
-1
3
}
# include_file {
..|..|altera|61|quartus|libraries|megafunctions|aglobal61.inc
b513fb574ceb8f5886cd4ba429e82ec
..|..|altera|61|quartus|libraries|others|maxplus2|memmodes.inc
44d4551a35f349f0dbacaf799d39950
..|..|altera|61|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|altera|61|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|altera|61|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
..|..|altera|61|quartus|libraries|megafunctions|altsyncram.inc
fcd2728179d3106e487da887737a8940
}
# hierarchies {
lpm_rom:i_rom|altrom:srom
}
# end
# entity
altsyncram
# storage
db|ddsc.(3).cnf
db|ddsc.(3).cnf
# case_insensitive
# source_file
..|..|altera|61|quartus|libraries|megafunctions|altsyncram.tdf
82b9e86c1df4d3a925c3859b8da0bf
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_UNKNOWN
USR
WIDTHAD_A
10
PARAMETER_UNKNOWN
USR
NUMWORDS_A
1024
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
sin_rom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_hb01
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|altera|61|quartus|libraries|megafunctions|aglobal61.inc
b513fb574ceb8f5886cd4ba429e82ec
..|..|altera|61|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|altera|61|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|altera|61|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|altera|61|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
..|..|altera|61|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|altera|61|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|altera|61|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|altera|61|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
}
# hierarchies {
lpm_rom:i_rom|altrom:srom|altsyncram:rom_block
}
# end
# entity
altsyncram_hb01
# storage
db|ddsc.(4).cnf
db|ddsc.(4).cnf
# case_insensitive
# source_file
db|altsyncram_hb01.tdf
fff2783925775307f2fc43572a5f43d
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
sin_rom.mif
361d3ea82762397943154aff5d8cd2
}
# hierarchies {
lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated
}
# end
# complete