ddsc.fit.summary

来自「DDS数字频率合成器」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Tue May 12 15:41:49 2009
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : ddsc
Top-level Entity Name : ddsc
Family : Cyclone II
Device : EP2C20Q240C8
Timing Models : Final
Total logic elements : 32 / 18,752 ( < 1 % )
    Total combinational functions : 32 / 18,752 ( < 1 % )
    Dedicated logic registers : 32 / 18,752 ( < 1 % )
Total registers : 32
Total pins : 43 / 142 ( 30 % )
Total virtual pins : 0
Total memory bits : 10,240 / 239,616 ( 4 % )
Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )