ddsc.fit.smsg

DDS数字频率合成器

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue May 12 15:41:43 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ddsc -c ddsc
Info: Selected device EP2C20Q240C8 for design "ddsc"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 4
    Info: Pin ~nCSO~ is reserved at location 5
    Info: Pin ~LVDS91p/nCEO~ is reserved at location 127
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 43 pins of 43 total pins
    Info: Pin ddsout[0] not assigned to an exact location on the device
    Info: Pin ddsout[1] not assigned to an exact location on the device
    Info: Pin ddsout[2] not assigned to an exact location on the device
    Info: Pin ddsout[3] not assigned to an exact location on the device
    Info: Pin ddsout[4] not assigned to an exact location on the device
    Info: Pin ddsout[5] not assigned to an exact location on the device
    Info: Pin ddsout[6] not assigned to an exact location on the device
    Info: Pin ddsout[7] not assigned to an exact location on the device
    Info: Pin ddsout[8] not assigned to an exact location on the device
    Info: Pin ddsout[9] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin freqin[22] not assigned to an exact location on the device
    Info: Pin freqin[21] not assigned to an exact location on the device
    Info: Pin freqin[20] not assigned to an exact location on the device
    Info: Pin freqin[19] not assigned to an exact location on the device
    Info: Pin freqin[18] not assigned to an exact location on the device
    Info: Pin freqin[17] not assigned to an exact location on the device
    Info: Pin freqin[16] not assigned to an exact location on the device
    Info: Pin freqin[15] not assigned to an exact location on the device
    Info: Pin freqin[14] not assigned to an exact location on the device
    Info: Pin freqin[13] not assigned to an exact location on the device
    Info: Pin freqin[12] not assigned to an exact location on the device
    Info: Pin freqin[11] not assigned to an exact location on the device
    Info: Pin freqin[10] not assigned to an exact location on the device
    Info: Pin freqin[9] not assigned to an exact location on the device
    Info: Pin freqin[8] not assigned to an exact location on the device
    Info: Pin freqin[7] not assigned to an exact location on the device
    Info: Pin freqin[6] not assigned to an exact location on the device
    Info: Pin freqin[5] not assigned to an exact location on the device
    Info: Pin freqin[4] not assigned to an exact location on the device
    Info: Pin freqin[3] not assigned to an exact location on the device
    Info: Pin freqin[2] not assigned to an exact location on the device
    Info: Pin freqin[1] not assigned to an exact location on the device
    Info: Pin freqin[0] not assigned to an exact location on the device
    Info: Pin freqin[23] not assigned to an exact location on the device
    Info: Pin freqin[24] not assigned to an exact location on the device
    Info: Pin freqin[25] not assigned to an exact location on the device
    Info: Pin freqin[26] not assigned to an exact location on the device
    Info: Pin freqin[27] not assigned to an exact location on the device
    Info: Pin freqin[28] not assigned to an exact location on the device
    Info: Pin freqin[29] not assigned to an exact location on the device
    Info: Pin freqin[30] not assigned to an exact location on the device
    Info: Pin freqin[31] not assigned to an exact location on the device
Info: Automatically promoted node clk (placed in PIN 34 (CLK2, LVDSCLK1p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 42 (unused VREF, 3.30 VCCIO, 32 input, 10 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  18 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  14 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  18 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  20 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  17 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  16 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  18 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.572 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y20; Fanout = 2; REG Node = 'acc[0]'
    Info: 2: + IC(0.675 ns) + CELL(0.596 ns) = 1.271 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[0]~160'
    Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.357 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[1]~161'
    Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.443 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[2]~162'
    Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.529 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[3]~163'
    Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.615 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[4]~164'
    Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.701 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[5]~165'
    Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.787 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[6]~166'
    Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.873 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[7]~167'
    Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.959 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[8]~168'
    Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.045 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[9]~169'
    Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.131 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[10]~170'
    Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.217 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[11]~171'
    Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.303 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[12]~172'
    Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.389 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[13]~173'
    Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.475 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[14]~174'
    Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.561 ns; Loc. = LAB_X16_Y20; Fanout = 2; COMB Node = 'acc[15]~175'
    Info: 18: + IC(0.107 ns) + CELL(0.086 ns) = 2.754 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[16]~176'
    Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.840 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[17]~177'
    Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 2.926 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[18]~178'
    Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.012 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[19]~179'
    Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.098 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[20]~180'
    Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.184 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[21]~181'
    Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.270 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[22]~182'
    Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.356 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[23]~183'
    Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.442 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[24]~184'
    Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.528 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[25]~185'
    Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.614 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[26]~186'
    Info: 29: + IC(0.000 ns) + CELL(0.086 ns) = 3.700 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[27]~187'
    Info: 30: + IC(0.000 ns) + CELL(0.086 ns) = 3.786 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[28]~188'
    Info: 31: + IC(0.000 ns) + CELL(0.086 ns) = 3.872 ns; Loc. = LAB_X16_Y19; Fanout = 2; COMB Node = 'acc[29]~189'
    Info: 32: + IC(0.000 ns) + CELL(0.086 ns) = 3.958 ns; Loc. = LAB_X16_Y19; Fanout = 1; COMB Node = 'acc[30]~190'
    Info: 33: + IC(0.000 ns) + CELL(0.506 ns) = 4.464 ns; Loc. = LAB_X16_Y19; Fanout = 1; COMB Node = 'acc[31]~137'
    Info: 34: + IC(0.000 ns) + CELL(0.108 ns) = 4.572 ns; Loc. = LAB_X16_Y19; Fanout = 11; REG Node = 'acc[31]'
    Info: Total cell delay = 3.790 ns ( 82.90 % )
    Info: Total interconnect delay = 0.782 ns ( 17.10 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location X12_Y14 to location X24_Y27
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 10 output pins without output pin load capacitance assignment
    Info: Pin "ddsout[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddsout[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddsout[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddsout[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddsout[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddsout[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddsout[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddsout[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddsout[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ddsout[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 230 megabytes of memory during processing
    Info: Processing ended: Tue May 12 15:41:49 2009
    Info: Elapsed time: 00:00:06