ddsc.qsf

DDS数字频率合成器

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		ddsc_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY ddsc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:15:10  MAY 30, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 6.1
set_global_assignment -name USER_LIBRARIES "H:/edasoftware/megcore/fir_compiler-v3.1.0/lib/;H:/edasoftware/megcore/nco-v2.2.1/lib/;H:\\edasoftware\\megcore\\fir_compiler-v3.2.0\\lib/;H:/edasoftware/megcore/nco-v2.3.0/lib/"
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE ANY
set_global_assignment -name VHDL_FILE ddsc.vhd
set_global_assignment -name MIF_FILE sin_rom.mif
set_global_assignment -name VECTOR_WAVEFORM_FILE ddsc.vwf
set_global_assignment -name VECTOR_TABLE_OUTPUT_FILE ddsc_sim.tbl
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"