📄 ddsc.vho

📁 DDS数字频率合成器
💻 VHO
📖 第 1 页 / 共 5 页
字号:
上一页 1 2 3 45
	datain => \acc[29]~135\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => acc(29));

\acc[30]~136_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \acc[30]~136\ = (\freqin~combout\(30) $ acc(30) $ !\acc[29]~189\) # GND
-- \acc[30]~190\ = CARRY(\freqin~combout\(30) & (acc(30) # !\acc[29]~189\) # !\freqin~combout\(30) & acc(30) & !\acc[29]~189\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100110001110",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \freqin~combout\(30),
	datab => acc(30),
	datad => VCC,
	cin => \acc[29]~189\,
	combout => \acc[30]~136\,
	cout => \acc[30]~190\);

\acc[30]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \acc[30]~136\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => acc(30));

\freqin[31]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(31),
	combout => \freqin~combout\(31));

\acc[31]~137_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \acc[31]~137\ = acc(31) $ \acc[30]~190\ $ \freqin~combout\(31)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100111100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => acc(31),
	datad => \freqin~combout\(31),
	cin => \acc[30]~190\,
	combout => \acc[31]~137\);

\acc[31]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \acc[31]~137\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => acc(31));

\i_rom|srom|rom_block|auto_generated|ram_block1a0\ : cycloneii_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init1 => X"FC9630D9630DA740DA741EB741EB852FC852FC9630DA741EB852FC9630DA741EB8630DA742FC9631EB8630DB8530DB8530EB8631EC9742FDA8631ECA7530ECA7531FCA86420EC97531FECA86420EDB976420FDBA865320FDCA9765320FECBA97654320FEDCBA98765443210FFEDCCBAA9987766554443332221111000000000000000000001111122233344556677889AABBCDEEF01123456789ABCDEF012346789BCDE0124578ABCEF134679BCE013568ACEF13579BDF02468BDF13579BD02469BDF2469BD02479CE1358AD0257ACF1479CF1479CF247ADF258AD0369CE147AD0369BE147AD0369CF258BE158BE147AD0369D0369CF259CF258BF258BE148BE",
	mem_init0 => X"147BE147AD047AD036AD0369CF269CF258BE147AE147AD0369CF258BE1469CF258BE1369CF257AD0258BD0368BE0368BE0358ADF257ACE1368BDF2469BD02469BDF2468ACE02479BDF02468ACE013579ACEF134689BCE0134578ABDEF12346789BCDEF0123456789ABCDEEF0112344556778899AABBCCCDDDEEEEEFFFFFFFFFFFFFFFFFFFFEEEEDDDCCCBBBAA9988766554332100FEDCBBA9876543210FDCBA98654310FDCA9865320FDCA975420FDB986421FDB975310ECA8631FDB97530ECA8531FCA8531EC97520DB8631EC9741FCA742FCA742FC9741EC9630DB852FC9741EB852FC9630DA741EB852FC9630DA730DA741EB841EB852FB852FC962FC9630",
	data_interleave_offset_in_bits => 1,
	data_interleave_width_in_bits => 1,
	init_file => "sin_rom.mif",
	init_file_layout => "port_a",
	logical_ram_name => "lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|ALTSYNCRAM",
	operation_mode => "rom",
	port_a_address_clear => "none",
	port_a_address_width => 10,
	port_a_byte_enable_clear => "none",
	port_a_byte_enable_clock => "none",
	port_a_data_in_clear => "none",
	port_a_data_out_clear => "none",
	port_a_data_out_clock => "none",
	port_a_data_width => 4,
	port_a_first_address => 0,
	port_a_first_bit_number => 0,
	port_a_last_address => 1023,
	port_a_logical_ram_depth => 1024,
	port_a_logical_ram_width => 10,
	port_a_write_enable_clear => "none",
	port_a_write_enable_clock => "none",
	port_b_address_width => 10,
	port_b_data_width => 4,
	ram_block_type => "M4K",
	safe_write => "err_on_2clk")
-- pragma translate_on
PORT MAP (
	clk0 => \clk~clkctrl\,
	portaaddr => \i_rom|srom|rom_block|auto_generated|ram_block1a0_PORTAADDR_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portadataout => \i_rom|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus\);

\i_rom|srom|rom_block|auto_generated|ram_block1a4\ : cycloneii_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init1 => X"FFFFFFEEEEEDDDDDCCCCCBBBBBAAAAA9999988888877777666665555554444433333322222111111000000FFFFFFEEEEEEDDDDDDCCCCCCBBBBBBBAAAAAAA9999999888888887777777666666666555555555444444444433333333333222222222222211111111111111111000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111222222222222233333333333344444444455555555556666666677777777888888899999999AAAAAABBBBBBBCCCCCCDDDDDDDEEEEEEFFFFFF000000111112222223333344444455555666666777778888899999AAAAABBBBBBCCCCCDDDDDEEEEEFFFFF",
	mem_init0 => X"0000011111222223333344444455555666667777788888999999AAAAABBBBBBCCCCCDDDDDDEEEEEFFFFFF000000111111222222233333344444445555556666666677777778888888899999999AAAAAAAAAABBBBBBBBBCCCCCCCCCCCCDDDDDDDDDDDDDEEEEEEEEEEEEEEEEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDCCCCCCCCCCCBBBBBBBBBBAAAAAAAAA999999999888888877777777666666655555554444444333333222222111111000000FFFFFFEEEEEEDDDDDCCCCCCBBBBBAAAAAA9999988888777777666665555544444333332222211111000000",
	data_interleave_offset_in_bits => 1,
	data_interleave_width_in_bits => 1,
	init_file => "sin_rom.mif",
	init_file_layout => "port_a",
	logical_ram_name => "lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|ALTSYNCRAM",
	operation_mode => "rom",
	port_a_address_clear => "none",
	port_a_address_width => 10,
	port_a_byte_enable_clear => "none",
	port_a_byte_enable_clock => "none",
	port_a_data_in_clear => "none",
	port_a_data_out_clear => "none",
	port_a_data_out_clock => "none",
	port_a_data_width => 4,
	port_a_first_address => 0,
	port_a_first_bit_number => 0,
	port_a_last_address => 1023,
	port_a_logical_ram_depth => 1024,
	port_a_logical_ram_width => 10,
	port_a_write_enable_clear => "none",
	port_a_write_enable_clock => "none",
	port_b_address_width => 10,
	port_b_data_width => 4,
	ram_block_type => "M4K",
	safe_write => "err_on_2clk")
-- pragma translate_on
PORT MAP (
	clk0 => \clk~clkctrl\,
	portaaddr => \i_rom|srom|rom_block|auto_generated|ram_block1a4_PORTAADDR_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portadataout => \i_rom|srom|rom_block|auto_generated|ram_block1a4_PORTADATAOUT_bus\);

\i_rom|srom|rom_block|auto_generated|ram_block1a8\ : cycloneii_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init0 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555550000000000000000000000000000000000000000000",
	data_interleave_offset_in_bits => 1,
	data_interleave_width_in_bits => 1,
	init_file => "sin_rom.mif",
	init_file_layout => "port_a",
	logical_ram_name => "lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|ALTSYNCRAM",
	operation_mode => "rom",
	port_a_address_clear => "none",
	port_a_address_width => 10,
	port_a_byte_enable_clear => "none",
	port_a_byte_enable_clock => "none",
	port_a_data_in_clear => "none",
	port_a_data_out_clear => "none",
	port_a_data_out_clock => "none",
	port_a_data_width => 2,
	port_a_first_address => 0,
	port_a_first_bit_number => 0,
	port_a_last_address => 1023,
	port_a_logical_ram_depth => 1024,
	port_a_logical_ram_width => 10,
	port_a_write_enable_clear => "none",
	port_a_write_enable_clock => "none",
	port_b_address_width => 10,
	port_b_data_width => 2,
	ram_block_type => "M4K",
	safe_write => "err_on_2clk")
-- pragma translate_on
PORT MAP (
	clk0 => \clk~clkctrl\,
	portaaddr => \i_rom|srom|rom_block|auto_generated|ram_block1a8_PORTAADDR_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portadataout => \i_rom|srom|rom_block|auto_generated|ram_block1a8_PORTADATAOUT_bus\);

\ddsout[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|auto_generated|q_a\(0),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ddsout(0));

\ddsout[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|auto_generated|q_a\(1),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ddsout(1));

\ddsout[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|auto_generated|q_a\(2),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ddsout(2));

\ddsout[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|auto_generated|q_a\(3),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ddsout(3));

\ddsout[4]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|auto_generated|q_a\(4),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ddsout(4));

\ddsout[5]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|auto_generated|q_a\(5),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ddsout(5));

\ddsout[6]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|auto_generated|q_a\(6),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ddsout(6));

\ddsout[7]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|auto_generated|q_a\(7),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ddsout(7));

\ddsout[8]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|auto_generated|q_a\(8),
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ddsout(8));

\ddsout[9]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \i_rom|srom|rom_block|aut
上一页 1 2 3 45
💿 文件大小 642 K
👤 上传用户 x8610341
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#DDS #数字频率合成器
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -